CP3BT23_14 Datasheet, PDF (240/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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If software loads the TWMT0 register with a new value, the timer uses that value the next time that it
reloads the 16-bit timer register (in other words, after reaching zero). Software can restart the timer at any
time (on the very next edge of the T0IN clock) by setting the Restart (RST) bit in the T0CSR register. The
T0CSR.RST bit is cleared automatically upon restart of the 16-bit timer.
Note: To enter Power Save or Idle mode after setting the T0CSR.RST bit, software must wait for the reset
operation to complete before performing the switch.
24.3 WATCHDOG OPERATION
The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At
reset, the Watchdog is disabled; it does not count and no Watchdog signal is generated. A write to either
the Watchdog Count (WDCNT) register or the Watchdog Service Data Match (WDSDM) register starts the
counter. The Watchdog counter counts down from the value programmed in the WDCNT register. Once
started, only a reset can stop the Watchdog from operating.
The Watchdog can be programmed to use either T0OUT or T0IN as its clock source (the output and input
of Timer T0, respectively). The TWCFG.WDCT0I bit controls this clock selection.
Software must periodically “service” the Watchdog. There are two ways to service the Watchdog, the
choice depending on the programmed value of the WDSDME bit in the Timer and Watchdog Configuration
(TWCFG) register.
If the TWCFG.WDSDME bit is clear, the Watchdog is serviced by writing a value to the WDCNT register.
The value written to the register is reloaded into the Watchdog counter. The counter then continues
counting down from that value.
If the TWCFG.WDSDME bit is set, the Watchdog is serviced by writing the value 5Ch to the Watchdog
Service Data Match (WDSDM) register. This reloads the Watchdog counter with the value previously
programmed into the WDCNT register. The counter then continues counting down from that value.
A Watchdog error signal is generated by any of the following events:
• The Watchdog serviced too late.
• The Watchdog serviced too often.
• The WDSDM register is written with a value other than 5Ch when WDSDM type servicing is enabled
(TWCFG.WDSDME = 1).
A Watchdog error condition resets the device.
24.3.1 Register Locking
The Timer and Watchdog Configuration (TWCFG) register is used to set the Watchdog configuration. It
controls the Watchdog clock source (T0IN or T0OUT), the type of Watchdog servicing (using WDCNT or
WDSDM), and the locking state of the TWCFG, TWCPR, TIMER0, T0CSR, and WDCNT registers. A
register that is locked cannot be read or written. A write operation is ignored and a read operation returns
unpredictable results.
If the TWCFG register is itself locked, it remains locked until the device is reset. Any other locked registers
also remain locked until the device is reset. This feature prevents a runaway program from tampering with
the programmed Watchdog function.
24.3.2 Power Save Mode Operation
The Timer and Watchdog Module is active in both the Power Save and Idle modes. The clocks and
counters continue to operate normally in these modes. The WDSDM register is accessible in the Power
Save and Idle modes, but the other TWM registers are accessible only in the Active mode. Therefore,
Watchdog servicing must be carried out using the WDSDM register in the Power Save or Idle mode.
In the Halt mode, the entire device is frozen, including the Timer and Watchdog Module. On return to
Active mode, operation of the module resumes at the point at which it was stopped.
240 Timing and Watchdog Module
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