CP3BT23_14 Datasheet, PDF (25/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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STORi
Mnemonic
STORD
STOR IMM
LOADM
LOADMP
STORM
STORMP
DI
EI
EIWAIT
NOP
WAIT
CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 5-2. Instruction Set Summary (continued)
Operands
Rsrc, disp(Rbase)
Rsrc, disp(RPbase)
Rsrc, abs
Rsrc, (Rindex)disp(RPbasex)
Rsrc, (Rindex)abs
RPsrc, disp(Rbase)
RPsrc, disp(RPbase)
RPsrc, abs
RPsrc, (Rindex)disp(RPbasex)
RPsrc, (Rindex)abs
imm4, disp(Rbase)
imm4, disp(RPbase)
imm4, (Rindex)disp(RPbasex)
imm4, abs
imm4, (Rindex)abs
imm3
imm3
STORM imm3
imm3
Description
Store (register relative)
Store (register pair relative)
Store (absolute)
Store (register pair relative index)
Store (absolute index)
Store (register relative)
Store (register pair relative)
Store (absolute)
Store (register pair index relative)
Store (absolute index relative)
Store unsigned 4-bit immediate value
extended to operand length in memory
Load 1 to 8 registers (R2-R5, R8-R11) from
memory starting at (R0)
Load 1 to 8 registers (R2-R5, R8-R11) from
memory starting at (R1, R0)
Store 1 to 8 registers (R2-R5, R8-R11) to
memory starting at (R2)
Store 1 to 8 registers (R2-R5, R8-R11) to
memory starting at (R7,R6)
Disable maskable interrupts
Enable maskable interrupts
Enable maskable interrupts and wait for
interrupt
No operation
Wait for interrupt
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CPU Architecture
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