CP3BT23_14 Datasheet, PDF (245/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
25 Multi-Function Timer
The Multi-Function Timer module contains a pair of 16-bit timer/counters. Each timer/counter unit offers a
choice of clock sources for operation and can be configured to operate in any of the following modes:
• Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a general-purpose timer/counter.
• Dual-Input Capture mode, which measures the elapsed time between occurrences of external events,
and which also provides a general-purpose timer/counter.
• Dual Independent Timer mode, which generates system timing signals or counts occurrences of
external events.
• Single-Input Capture and Single Timer mode, which provides one external event counter and one
system timer.
The timer unit uses two I/O pins, called TA and TB. The timer I/O pins are alternate functions of the PG7
and PE4 port pins, respectively.
25.1 TIMER STRUCTURE
Figure 25-1 is a block diagram showing the internal structure of the MFT. There are two main functional
blocks: a Timer/ Counter and Action block and a Clock Source block. The Timer/Counter and Action block
contains two separate timer/counter units, called Timer/Counter 1 and Timer/Counter
Clock Source
PCLK
Clock
Timer/Counter
Reload/Capture A
TCRA_n
Timer/Counter 1
TCNT1_n
Reload/Capture B
TCRB_n
Timer/Counter 2
TCNT2_n
Action
TAn
Interrupt A
Interrupt B
TBn
External Event
PWM/Capture/Counter
Mode Select + Control
DS448
Figure 25-1. Multi-Function Timer Block Diagram
25.1.1 Timer/Counter Block
The Timer/Counter block contains the following functional blocks:
• Two 16-bit counters, Timer/Counter 1 (TCNT1) and Timer/Counter 2 (TCNT2)
• Two 16-bit reload/capture registers, TCRA and TCRB
• Control logic necessary to configure the timer to operate in any of the four operating modes
• Interrupt control and I/O control logic
In a power-saving mode that uses the low-frequency (32.768 kHz) clock as the System Clock, the
synchronization circuit requires that the Slow Clock operate at no more than one-fourth the speed of the
32.768 kHz System Clock.
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