CP3BT23_14 Datasheet, PDF (45/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
CWD
DISVRF
IENPROG
PER
MER
The CPU Write Disable bit controls whether the CPU has write access to flash memory.
This bit must not be changed while FMBUSY is set.
0 – The CPU has write access to the flash memory
1 – An external debugging tool is the current “owner” of the flash memory interface, so write
accesses by the CPU are inhibited.
The Disable Verify bit controls the automatic verification feature. This bit must not be
changed while the flash program memory is busy being programmed or erased.
0 – New flash program memory contents are automatically verified after programming.
1 – Automatic verification is disabled.
The Interrupt Enable for Program bit is clear after reset. The flash program and data
memories share a single interrupt channel but have independent interrupt enable control
bits.
0 – No interrupt request is asserted to the ICU when the FMFULL bit is cleared.
1 – An interrupt request is made when the FMFULL bit is cleared and new data can be
written into the write buffer.
The Program Enable bit controls write access of the CPU to the flash program memory.
This bit must not be altered while the flash program memory is busy being programmed or
erased. The PER and MER bits must be clear when this bit is set.
0 – Programming the flash program memory by the CPU is disabled.
1 – Programming the flash program memory is enabled.
The Module Erase Enable bit controls whether a valid write operation triggers an erase
operation on an entire block of flash memory. If an information block is written in this mode,
both the information block and its corresponding main block are erased. When the MER bit
is set, the PE and PER bits must be clear. This bit must not be changed while the flash
program memory is busy being programmed or erased.
0 – Module erase mode disabled. Write operations are performed normally.
1 – A valid write operation to a word location in a main block erases the block that contains
the word. A valid write operation to a word location in an information block erases the block
that contains the word and its associated main block.
8.5.7 Flash Memory Status Register (FMSTAT/ FSMSTAT)
This register reports the currents status of the on-chip Flash memory. The FLSR register is clear after
device reset. The CPU bus master has read/write access to this register.
7
5
Reserved
4
DERR
3
FMFULL
2
FMBUSY
1
PERR
0
EERR
EERR
PERR
The Erase Error bit indicates whether an error has occurred during a page erase or module
(block) erase. After an erase error occurs, software can clear the EERR bit by writing a 1 to
it. Writing a 0 to the EERR bit has no effect. Software must not change this bit while the
flash program memory is busy being programmed or erased.
0 – The erase operation was successful.
1 – An erase error occurred.
The Program Error bit indicates whether an error has occurred during programming. After a
programming error occurs, software can clear the PERR bit by writing a 1 to it. Writing a 0
to the PERR bit has no effect. Software must not change this bit while the flash program
memory is busy being programmed or erased.
0 – The programming operation was successful.
1 – A programming error occurred.
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