CP3BT23_14 Datasheet, PDF (115/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
ADCIN
DIFF
The ADCIN bit selects the source of the ADC input. When the bit is clear, the source is the 8-
channel Input Multiplexer. When the bit is set, the source is the ADCIN pin.
0 – ADC input is from 8-channel multiplexer.
1 – ADC input is from ADCIN pin.
The Differential Operation Mode bit and the MUX_CFG field configure the analog circuits of
the ADC module. When this bit is clear, the ADC module operates in single-ended mode.
When this bit is set, the ADC operates in differential mode. See Table 16-2.
0 – Single-ended mode.
1 – Differential mode.
MUX_CFG
000
001
010
011
100
101
110
111
Table 16-2. MUX_CFG Operation
Channel Selected, (DIFF = 0)
0
1
2
3
4
5
6
7
Channels Selected (DIFF = 1)
+
-
0
1
1
0
2
3
3
2
4
5
5
4
6
7
7
6
For best noise immunity in touchscreen applications, channel 2 should be used for sampling the X plate
voltage, and channel 1 should be used for sampling the Y plate voltage.
TOUCH_C
FG
The Touchscreen Configuration field controls the configuration of the low-ohmic drivers for
the TSX+, TSX-, TSY+, and TSYsignals, as shown in Table 16-3. When TOUCH_CFG is
101b, the pen-down detector is enabled. The output of the pen-down detector is visible to
software in the PEN_DOWN bit of the ADSRESLT register, and it is ORed with the Done
signal to generate the wake-up signal WUI30 passed to the MIWU unit.
TOUCH_CF
G
000
001
010
011
100
101
11X
ADC0/TSX+
Inactive
Inactive
Driven High
Driven High
Inactive
Weakly Pulled High
Inactive
Table 16-3. TOUCH_CFG Modes
ADC1/TSY+
Inactive
Driven High
Inactive
Inactive
Driven High
Inactive
Inactive
ADC2/TSX-
Inactive
Inactive
Driven Low
Inactive
Driven Low
Inactive
Inactive
ADC3/TSY-
Inactive
Driven Low
Inactive
Driven Low
Inactive
Driven Low
inactive
Mode
None
Sample Y
Sample X
Sample Z (1), Pre-Pen
Down
Sample Z (2)
Pen-Down Detect
Reserved
PREF_CFG The Positive Voltage Reference Configuration field specifies the source of the ADC positive
voltage reference, according to the following table:
PREF_CFG
00
01
Table 16-4.
PREF Source
Internal (AVCC)
VREFP
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