CP3BT23_14 Datasheet, PDF (48/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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8.5.14 Flash Memory End Time Reload Register (FMEND/FSMEND)
The FMEND/FSMEND register is a byte-wide read/write register that controls the delay time after a
program/erase operation. Software must not modify this register while a program/erase operation is in
progress (FMBUSY set). At reset, this register is initialized to 18h when the flash memory on the chip is
idle. The CPU bus master has read/write access to this register.
7
0
FTEND
FTEND
The Flash Timing End Delay Count field specifies a delay of (FTEND + 1) prescaler output
clocks.
8.5.15 Flash Memory Module Erase End Time Reload Register (FMMEND/FSMMEND)
The FMMEND/FSMMEND register is a byte-wide read/write register that controls the delay time after a
module erase operation. Software must not modify this register while a program/erase operation is in
progress (FMBUSY set). At reset, this register is initialized to 3Ch if the flash memory is idle. The CPU
bus master has read/write access to this register.
7
0
FTMEND
FTMEND The Flash Timing Module Erase End Delay Count field specifies a delay of 8 × (FTMEND +
1) prescaler output clocks.
8.5.16 Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV)
The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time
between two flash memory accesses. Software must not modify this register while a program/erase
operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is
idle. The CPU bus master has read/write access to this register.
7
0
FTRCV
FTRCV
The Flash Timing Recovery Delay Count field specifies a delay of (FTRCV + 1) prescaler
output clocks.
8.5.17 Flash Memory Auto-Read Register 0 (FMAR0/ FSMAR0)
The FMAR0/FSMAR0 register contains a copy of the Function Word from Information Block 0. The
Function Word is sampled at reset. The CPU bus master has read-only access to this register. The
FSMAR0 register has the same value as the FMAR0 register
15
0
Reserved
48
Flash Memory
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