CP3BT23_14 Datasheet, PDF(14/324 Page) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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CP3BT23_14 Datasheet, PDF (14/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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CP3BT23

SNOSCX3A â JULY 2013 â REVISED JANUARY 2014

www.ti.com

Name

PH3

PH4

PH5

PH6

PH7

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

Table 4-1. CP3BT23 LQFP-128 Signal Descriptions (continued)

Pins

1

1

1

1

1

1

1

1

1

1

1

1

1

I/O

Primary Function

Alternate

Name

Alternate Function

I/O Generic I/O

TXD2

UART Channel 2 Transmit Data Output

WUI14

Multi-Input Wake-Up Channel 14

I/O Generic I/O

RXD3

UART Channel 3 Receive Data Input

WUI15

Multi-Input Wake-Up Channel 15

I/O Generic I/O

TXD3

UART Channel 3 Transmit Data Output

WUI16

Multi-Input Wake-Up Channel 16

I/O Generic I/O

CAN0RX

CAN Receive Input

WUI17

Multi-Input Wake-Up Channel 17

I/O Generic I/O

CAN0TX

CAN Transmit Output

I/O Generic I/O

WUI18

Multi-Input Wake-Up Channel 18

I/O Generic I/O

WUI19

Multi-Input Wake-Up Channel 19

I/O Generic I/O

WUI20

Multi-Input Wake-Up Channel 20

I/O Generic I/O

WUI21

Multi-Input Wake-Up Channel 21

I/O Generic I/O

WUI22

Multi-Input Wake-Up Channel 22

I/O Generic I/O

WUI23

Multi-Input Wake-Up Channel 23

I/O Generic I/O

WUI24

Multi-Input Wake-Up Channel 24

I/O Generic I/O

ASYNC

Start convert signal to ADC

WUI9

Multi-Input Wake-Up Channel 9

Name

X1CKI

X1CKO

X2CKI

X2CKO

RESET

ENV0

ENV2

TMS

TCK

TDI

TDO

RDY

VCC

GND

IOVCC

Pins

1

1

1

1

1

1

1

1

1

1

1

1

6

6

10

Table 4-2. CP3BT23 LQFP-144 Signal Descriptions

I/O

Input

Output

Input

Output

Input

I/O

I/O

Input

Input

Input

Output

Output

Input

Input

Input

Primary Function

Alternate

Name

12 MHz Oscillator Input BBCLK

12 MHz Oscillator

Output

None

32 kHz Oscillator Input None

32 kHz Oscillator

Output

None

Chip general reset

None

Special mode select PLLCLK

input with internal pull-

up during reset

Special mode select SLOWCLK

input with internal pull-

up during reset

JTAG Test Mode

Select (with internal

weak pull-up)

None

JTAG Test Clock Input None

(with internal weak pull-

up)

JTAG Test Data Input None

(with internal weak pull-

up)

JTAG Test Data Output None

NEXUS Ready Output None

2.5V Core Logic Power None

Supply

Core Ground

None

2.5â3.3V I/O Power

Supply

None

Alternate Function

BB reference clock for the RF Interface

None

None

None

None

PLL Clock Output

Slow Clock Output

None

None

None

None

None

None

None

None

14

Signal Descriptions

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