CP3BT23_14 Datasheet, PDF (212/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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21.3.8 UART Interrupt Control Register (UnICTRL)
The UnICTRL register is a byte-wide register that contains the receive and transmit interrupt status bits
(read-only bits) and the interrupt enable bits (read/write bits). The register is initialized to 01h at reset. The
register format is shown below.
7
UEEI
6
UERI
5
UETI
4
UEFCI
3
UCTS
2
UDCTS
1
URBF
0
UTBE
UTBE
URBF
UDCTS
UCTS
UEFCI
UETI
UERI
UEEI
The Transmit Buffer Empty bit is set by hardware when the UART transfers data from the
UnTBUF register to the transmit shift register for transmission. It is automatically cleared by
the hardware on the next write to the UnTBUF register.
0 – Transmit buffer is loaded.
1 – Transmit buffer is empty.
The Receive Buffer Full bit is set by hardware when the UART has received a complete
data frame and has transferred the data from the receive shift register to the UnRBUF
register. It is automatically cleared by the hardware when the UnRBUF register is read.
0 – Receive buffer is empty.
1 – Receive buffer is loaded.
The Delta Clear To Send bit indicates whether the CTS input has changed state since the
CPU last read this register. This functionality is only available for the UART0 module.
0 – No change since last read.
1 – State has changed since last read.
The Clear To Send bit indicates the state on the CTS input. This functionality is only
available for the UART0 module.
0 – CTS input is high.
1 – CTS input is low.
The Enable Flow Control Interrupt bit controls whether a flow control interrupt is generated
when the UDCTS bit changes from clear to set. This functionality is only available for the
UART0 module.
0 – Flow control interrupt disabled.
1 – Flow control interrupt enabled.
The Enable Transmitter Interrupt bit, when set, enables generation of an interrupt when the
hardware sets the UTBE bit.
0 – Transmit buffer empty interrupt disabled.
1 – Transmit buffer empty interrupt enabled.
The Enable Receiver Interrupt bit, when set, enables generation of an interrupt when the
hardware sets the URBF bit.
0 – Receive buffer full interrupt disabled.
1 – Receive buffer full interrupt enabled.
The Enable Receive Error Interrupt bit, when set, enables generation of an interrupt when
the hardware sets the UERR bit in the UnSTAT register.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
212 UART Modules
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