CP3BT23_14 Datasheet, PDF (253/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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Name
TCKC
TCNT
TCNT2
TCRA
TCRB
TCTRL
TICTL
TICLR
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 25-3. Multi-Function Timer Registers (continued)
Address
FF FF4Ah
FF FF40h
FF FF46h
FF FF42h
FF FF44h
FF FF4Ch
FF FF4Eh
FF FF50h
Description
Clock Unit Control Register
Timer/Counter 1 Register
Timer/Counter 2 Register
Reload/Capture A Register
Reload/Capture B Register
Timer Mode Control Register
Timer Interrupt Control Register
Timer Interrupt Clear Register
25.5.1 Clock Prescaler Register (TPRSC)
The TPRSC register is a byte-wide, read/write register that holds the current value of the 5-bit clock
prescaler (CLKPS). This register is cleared on reset. The register format is shown below.
7
5
4
0
Reserved
CLKPS
CLKPS
The Clock Prescaler field specifies the divisor used to generate the Timer Clock from the
System Clock. When the timer is configured to use the prescaled clock, the System Clock is
divided by (CLKPS + 1) to produce the timer clock. Therefore, the System Clock divisor can
range from 1 to 32.
25.5.2 Clock Unit Control Register (TCKC)
The TCKC register is a byte-wide, read/write register that selects the clock source for each timer/counter.
Selecting the clock source also starts the counter. This register is cleared on reset, which disables the
timer/counters. The register format is shown below.
7
6
Reserved
5
3
C2CSEL
2
0
C1CSEL
C1CSEL
C2CSEL
The Counter 1 Clock Select field specifies the clock mode for Timer/Counter 1 as follows:
000 – No clock (Timer/Counter 1 stopped, modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – External event on TB (modes 1 and 3 only).
011 – Pulse-accumulate mode based on TB (modes 1 and 3 only).
100 – Slow Clock.*
101 – Reserved.
110 – Reserved.
111 – Reserved.
The Counter 2 Clock Select field specifies the clock mode for Timer/Counter 2 as follows:
000 – No clock (Timer/Counter 2 stopped, modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – External event on TB (modes 1 and 3 only).
011 – Pulse-accumulate mode based on TB (modes 1 and 3 only). 100 – Slow Clock*
101 – Reserved.
110 – Reserved.
111 – Reserved.
* Operation of the Slow Clock is determined by the CRCTRL.SCLK control bit, as described in Section
11.9.1.
Copyright © 2013–2014, Texas Instruments Incorporated
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Multi-Function Timer 253