CP3BT23_14 Datasheet, PDF (73/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
POR
The Power-On-Reset bit is set when a powerturn-on condition has been detected. This bit
can only be cleared by software, not set. Writing a 1 to this bit will be ignored, and the
previous value of the bit will be unchanged.
0 – Software cleared this bit.
1 – Software has not cleared his bit since the last reset.
11.9.2 High Frequency Clock Prescaler Register (PRSFC)
The PRSFC register is a byte-wide read/write register that holds the 4-bit clock divisor used to generate
the high-frequency clock. In addition, the upper three bits are used to control the operation of the PLL. The
register is initialized to 4Fh at reset (except in PROG mode.)
7
6
4
3
0
Res.
MODE
FCDIV
FCDIV
MODE
The Fast Clock Divisor specifies the divisor used to obtain the high-frequency System Clock
from the PLL or Main Clock. The divisor is (FCDIV + 1).
The PLL MODE field specifies the operation mode of the on-chip PLL. After reset the MODE
bits are initialized to 100b, so the PLL is configured to generate a 48-MHz clock. This
register must not be modified when the System Clock is derived from the PLL Clock. The
System Clock must be derived from the low-frequency oscillator clock while the MODE field
is modified.
MODE 2:0
000
001
010
011
100
101
110
111
Table 11-4.
Output Frequency (from 12 MHz input clock)
Reserved
Reserved
Reserved
36 MHz
48 MHz
60 MHz
Reserved
Reserved
Description
Reserved
Reserved
Reserved
3x Mode
4x Mode
5x Mode
Reserved
Reserved
11.9.3 Low Frequency Clock Prescaler Register (PRSSC)
The PRSSC register is a byte-wide read/write register that holds the clock divisor used to generate the
Slow Clock from the Main Clock. The register is initialized to B6h at reset.
7
0
SCDIV
SCDIV
The Slow Clock Divisor field specifies a divisor to be used when generating the Slow Clock
from the Main Clock. The Main Clock is divided by a value of (2 × (SCDIV + 1)) to obtain
the Slow Clock. At reset, the SCDIV register is initialized to B6h, which generates a Slow
Clock rate of 32786.885 Hz. This is about 0.5% faster than a Slow Clock generated from an
external 32768 Hz crystal network.
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Triple Clock and Reset
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