CP3BT23_14 Datasheet, PDF (255/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
TAEN
TBEN
TAOUT
TEN
The TA Enable bit controls whether the TA pin is enabled to operate as a preset input or as
a PWM output, depending on the timer operating mode. In Mode 2 (Dual Input Capture), a
transition on the TA pin presets the TCNT1 counter to FFFFh. In the other modes, TA
functions as a PWM output. When this bit is clear, operation of the pin for the timer/counter
is disabled.
0 – TA input disabled.
1 – TA input enabled.
The TB Enable bit controls whether the TB pin in enabled to operate in Mode 2 (Dual Input
Capture) or Mode 4 (Single Input Capture and Single Timer). A transition on the TB pin
presets the corresponding timer/counter to FFFFh (TCNT1 in Mode 2 or TCNT2 in Mode 4).
When this bit is clear, operation of the pin for the timer/counter is disabled. This bit setting
has no effect in Mode 1 or Mode 3.
0 – TB input disabled.
1 – TB input enabled.
The TA Output Data bit indicates the current state of the TA pin when the pin is used as a
PWM output. The hardware sets and clears this bit, but software can also read or write this
bit at any time and therefore control the state of the output pin. In case of conflict, a
software write has precedence over a hardware update. This bit setting has no effect when
the TA pin is used as an input.
0 – TA pin is low.
1 – TA pin is high.
The Timer Enable bit controls whether the Multi-Function Timer is enabled. When the
module is disabled all clocks to the counter unit are stopped to minimize power
consumption. For that reason, the timer/counter registers (TCNT1 and TCNT2), the
capture/reload registers (TCRA and TCRB), and the interrupt pending bits (TXPND) cannot
be written in this mode. Also, the 5-bit clock prescaler and the interrupt pending bits are
cleared, and the TA I/O pin becomes an input.
0 – Multi-Function Timer is disabled.
1 – Multi-Function Timer is enabled.
25.5.8 Timer Interrupt Control Register (TICTL)
The TICTL register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt
pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes
each type of interrupt depends on the operating mode, as shown in Table 25-1.
This register is cleared upon reset. The register format is shown below.
7
TDIEN
6
TCIEN
5
TBIEN
4
TAIEN
3
TDPND
2
TCPND
1
TBPND
0
TAPND
TAPND
TBPND
The Timer Interrupt Source A Pending bit indicates that timer interrupt condition A has
occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 25-1. This bit
can be set by hardware or by software. To clear this bit, software must use the Timer
Interrupt Clear Register (TICLR). Attempting to directly write a 0 to this bit is ignored.
0 – Interrupt source A has not triggered.
1 – Interrupt source A has triggered.
The Timer Interrupt Source B Pending bit indicates that timer interrupt condition B has
occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 25-1. This bit
can be set by hardware or by software. To clear this bit, software must use the Timer
Interrupt Clear Register (TICLR). Attempting to directly write a 0 to this bit is ignored.
0 – Interrupt source B has not triggered.
1 – Interrupt source B has triggered.
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Multi-Function Timer 255