CP3BT23_14 Datasheet, PDF (87/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
13.1.9 Wake-Up Interrupt Control Register 2 (WK0ICTL2)
The WK0ICTL2 register is a word-wide read/write register that selects the interrupt request signal for the
associated MIWU channels WUI15:8. At reset, the WK2ICTL2 register is cleared, which selects MIWU
Interrupt Request 0 for all eight channels. The register format is shown below.
15
14
WKIN TR15
13
12
WKIN TR14
11
10
WKIN TR13
9
8
WKIN TR12
7
6
WKIN TR11
5
4
WKIN TR10
3
2
WKIN TR9
1
0
WKIN TR8
WKINTR
The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt
requests are activated for the corresponding channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
11 – Selects MIWU interrupt request 3.
13.1.10 Wake-Up 1 Interrupt Control Register 2 (WK1ICTL2)
The WK1ICTL2 register is a word-wide read/write register that selects the interrupt request signal for the
associated MIWU channels WUI31:24. At reset, the WK1ICTL2 register is cleared, which selects MIWU
Interrupt Request 4 for all eight channels. The register format is shown below.
15
14
WKIN TR31
13
12
WKIN TR30
11
10
WKIN TR29
9
8
WKIN TR28
7
6
WKIN TR27
5
4
WKIN TR26
3
2
WKIN TR25
1
0
WKIN TR24
WKINTR
The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt
requests are activated for the corresponding channel.
00 – Selects MIWU interrupt request 4.
01 – Selects MIWU interrupt request 5.
10 – Selects MIWU interrupt request 6.
11 – Selects MIWU interrupt request 7.
13.1.11 Wake-Up Pending Register (WK0PND)
The WK0PND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches
any detected trigger conditions. The CPU can only write a 1 to any bit position in this register. If the CPU
attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the
WK0PCL register. This implementation prevents a potential hardware-software conflict during a read-
modify-write operation on the WK0PND register.
This register is cleared upon reset. The register format is shown below.
15
0
WKPD
WKPD
The Wake-Up Pending bits indicate which MIWU channels have been triggered. The
WKPD15:0 bits correspond to the WUI15:0 channels. Writing 1 to a bit sets it.
0 – Trigger condition did not occur.
1 – Trigger condition occurred.
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