CP3BT23_14 Datasheet, PDF (206/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
21.2.7 Interrupts
The UART is capable of generating interrupts on:
• Receive Buffer Full
• Receive Error
• Transmit Buffer Empty
Figure 21-7 shows a diagram of the interrupt sources and associated enable bits.
UFE
UEEI
UDOE
UPE
UERR
UERI
RX
Interrupt
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URBF
UETI
UTBE
UEFCI
TX
Interrupt
UDCTS
Figure 21-7. UART Interrupts
FC
Interrupt
DS066
The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UETI), Enable
Receive Interrupt (UERI), and Enable Receive Error Interrupt (UEER) bits in the UnICTRL register.
A transmit interrupt is generated when both the UTBE and UETI bits are set. To remove this interrupt,
software must either disable the interrupt by clearing the UETI bit or write to the UnTBUF register (which
clears the UTBE bit).
A receive interrupt is generated on these conditions:
• Both the URBF and UERI bits are set. To remove this interrupt, software must either disable the
interrupt by clearing the UERI bit or read from the URBUF register (which clears the URBF bit).
• Both the UERR and the UEEI bits are set. To remove this interrupt, software must either disable the
interrupt by clearing the UEEI bit or read the UnSTAT register (which clears the UERR bit).
A flow control interrupt is generated when both the UDCTS and the UEFCI bits are set. To remove this
interrupt, software must either disable the interrupt by clearing the UEFCI bit or reading the UnICTRL
register (which clears the UDCTS bit).
In addition to the dedicated inputs to the ICU for UART interrupts, the UART receive (RXD) and Clear To
Send (CTS) signals are inputs to the MIWU (see Section Multi-Input Wake-Up), which can be
programmed to generate edge-triggered interrupts.
206 UART Modules
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