CP3BT23_14 Datasheet, PDF (185/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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FSL
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 19-3. START TABLES HERE
Frame Sync Length
13 bit clocks
14 bit clocks
15 bit clocks
16 bit clocks
IFS
IOM2
AAIEN
CLKEN
The Inverted Frame Sync bit controls the polarity of the frame sync signal.
0 – Active-high frame sync signal.
1 – Active-low frame sync signal.
The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used
to connect to external ISDN controller devices. The AAI can only operate as a slave in the
IOM-2 mode, i.e. the bit clock and frame sync signals are provided by the ISDN controller. If
the IOM2 bit is clear, the AAI operates in the normal PCM interface mode used to connect to
external PCM codecs and other PCM audio devices.
0 – IOM-2 mode disabled.
1 – IOM-2 mode enabled.
The AAI Enable bit controls whether the Advanced Audio Interface is enabled. All AAI
registers provide read/write access while (CLKEN = 1) AAIEN is clear. The AAIEN bit is clear
after reset.
0 – AAI module disabled.
1 – AAI module enabled.
The Clock Enable bit controls whether the Advanced Audio Interface clock is enabled. The
CLKEN bit must be set to allow access to any AAI register. It must also be set before any
other bit of the AGCR can be set. The CLKEN bit is clear after reset.
0 – AAI module clock disabled.
1 – AAI module clock enabled.
19.7.6 Audio Interrupt Status and Control Register (AISCR)
The ASCR register is used to specify the source and the conditions, when the audio interface interrupt is
asserted to the Interrupt Control Unit. It also holds the interrupt pending bits and the corresponding
interrupt clear bits for each audio interface interrupt source. The CPU bus master has read/ write access
to the ASCR register. After reset, this register is clear.
7
TXEIP
6
TXIP
5
RXEIP
4
RXIP
3
TXEIE
2
TXIE
1
RXEIE
0
RXIE
15
RXIE
RXEIE
Reserved
12
11
10
9
8
TXEIC
TXIC
RXEIC
RXIC
The Receive Interrupt Enable bit controls whether receive interrupts are generated. If the
RXIE bit is clear, no receive interrupt will be generated.
0 – Receive interrupt disabled.
1 – Receive interrupt enabled.
The Receive Error Interrupt Enable bit controls whether receive error interrupts are
generated. Setting this bit enables a receive error interrupt, when the Receive Buffer Overrun
(RXOR) bit is set. If the RXEIE bit is clear, no receive error interrupt will be generated.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
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Advanced Audio Interface 185