CP3BT23_14 Datasheet, PDF (90/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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14 Input/Output Ports
Each device has up to 50 software-configurable I/O pins, organized into 8-bit ports (not all bits are used in
some ports). The ports are named Port B, Port C, Port E, Port F, Port G, Port H, and Port J.
In addition to their general-purpose I/O capability, the I/O pins of Ports E, F, G, H, and J have alternate
functions for use with on-chip peripheral modules such as the UART or the Multi-Input Wake-Up unit. The
alternate functions of all I/O pins are shown in Table 30-1.
Ports B and C are used as the 16-bit data bus when an external bus is enabled (144-pin devices only).
This alternate function is selected by enabling the DEV or ERE operating environments, not by
programming the port registers.
The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-
STATE output, pushpull output, weak pull-up input, or high-impedance input.
Different pins within the same port can be individually configured to operate in different modes.
Figure 14-1 is a diagram showing the I/O port pin logic. The register bits, multiplexers, and buffers allow
the port pin to be configured into the various operating modes. The output buffer is a TRI-STATE buffer
with weak pull-up capability. The weak pull-up, if used, prevents the port pin from going to an undefined
state when it operates as an input.
To reduce power consumption, input buffers configured for general-purpose I/O are only enabled when
they are read. When configured for an alternate function, the input buffers are enabled continuously. To
minimize power consumption, input signals to enabled buffers must be held within 0.2 volts of the VCC or
GND voltage.
The electrical characteristics and drive capabilities of the input and output buffers are described in Section
29.0.
PxALTS Register
DQ
DQ
PxALT Register
DQ
PxWKPU Register
Alt. A Device Direction
Alt. B Device Direction
DQ
PxDIR Register
Alt. A Device Data Outout
Alt. B Device Data Outout
DQ
PxDOUT Register
VCC
Weak Pull-Up Enable
Output Enable
Pin
Data Out
Alt. A Data Input
PxDIN Register
Alt. B Data Input
Data In Read Strobe
Data In
1
Analog Input
Figure 14-1. I/O Port Pin Logic
DS190
90
Input/Output Ports
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