CP3BT23_14 Datasheet, PDF (43/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
8.5.1 Flash Memory Information Block Address Register (FMIBAR/FSMIBAR)
The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because
only word access to the information blocks is supported, the least significant bit (LSB) of the FMIBAR must
be 0 (word-aligned). The hardware automatically clears the LSB, without regard to the value written to the
bit. The FMIBAR register is cleared after device reset. The CPU bus master has read/write access to this
register.
15
8
7
Reserved
IBA
IBA
The Information Block Address field holds the word-aligned address of an information block
location accessed during a read or write transaction. The LSB of the IBA field is always
clear. xxx
8.5.2 Flash Memory Information Block Data Register (FMIBDR/FSMIBDR)
The FMIBDR register holds the 16-bit data for read or write access to an information block. The FMIBDR
register is cleared after device reset. The CPU bus master has read/ write access to this register.
15
0
IBD
IBD
The Information Block Data field holds the data word for access to an information block. For
write operations the IBD field holds the data word to be programmed into the information
block location specified by the IBA address. During a read operation from an information
block, the IBD field receives the data word read from the location specified by the IBA
address.
8.5.3 Flash Memory 0 Write Enable Register (FM0WER/FSM0WER)
The FM0WER register controls section-level write protection for the first half of the flash program memory.
The FMS0WER registers controls section-level write protection for the flash data memory. Each data block
is divided into 16 8K-byte sections. Each bit in the FM0WER and FSM0WER registers controls write
protection for one of these sections. The FM0WER and FSM0WER registers are cleared after device
reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to
this registers.
15
0
FMOWE
FM0WEn The Flash Memory 0 Write Enable n bits control write protection for a section of a flash
memory data block. The address mapping of the register bits is shown below.
Bit
0
1-14
15
Logical Address Range
00 0000h–00 1FFFh
...
01 E000h–01 FFFFh
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