CP3BT23_14 Datasheet, PDF (215/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
21.4 BAUD RATE CALCULATIONS
The UART baud rate is determined by the System Clock frequency and the values in the UnOVR, UnPSR,
and UnBAUD registers. Unless the System Clock is an exact multiple of the baud rate, there will be a
small amount of error in the resulting baud rate.
21.4.1 Asynchronous Mode
The equation to calculate the baud rate in asynchronous mode is:
BR = SYS_CLK / (O x N x P)
where
• BR is the baud rate,
• SYS_CLK is the System Clock,
• O is the oversample rate,
• N is the baud rate divisor + 1,
• P is the prescaler divisor selected by the UPSR register.
(26)
Assuming a System Clock of 5 MHz, a desired baud rate of 9600, and an oversample rate of 16, the N ×
P term according to the equation above is:
N x P = (5x10¹⁶) / (16 x 9600) = 32.552
(27)
The N × P term is then divided by each Prescaler Factor from Table 21-1 to obtain a value closest to an
integer. The factor for this example is 6.5.
N - 32.552 / 6.5 = 5.008
(28)
(N = 5)
The baud rate register is programmed with a baud rate divisor of 4 (N = baud rate divisor + 1). This
produces a baud clock of:
BR = (5 x 10⁶) / 16 x 5 x 6.5) = 9615.385
(29)
% error = (9615.385 - 9600) / 9600 = 0.16
(30)
Note that the percent error is much lower than would be possible without the non-integer prescaler factor.
Error greater than 3% is marginal and may result in unreliable operation. Refer to Table 21-5 below for
more examples.
(31)
21.4.2 Synchronous Mode
Synchronous mode is only available for the UART0 module. When synchronous mode is selected and the
UCKS bit is set, the UART operates from a clock received on the CKX pin. When the UCKS bit is clear,
the UART uses the clock from the internal baud rate generator which is also driven on the CKX pin. When
the internal baud rate generator is used, the equation for calculating the baud rate is:
(32)
where BR is the baud rate, SYS_CLK is the System Clock, N is the value of the baud rate divisor + 1, and
P is the prescaler divide factor selected by the value in the UnPSR register. Oversampling is not used in
synchronous mode.
Use the same procedure to determine the values of N and P as in the asynchronous mode. In this case,
however, only integer prescaler values are allowed.
Table 21-5. Baud Rate Programming
Baud
Rate
300
600
SYS_CLK = 48 MHz
O
N
P
%err
16
2000
5
0
16
2000
2.5
0
SYS_CLK = 24 MHz
O
N
P
%err
16
2000
2.5
0
16
1250
2
0
SYS_CLK = 12 MHz
O
N
P
%err
16
1250
2
0
16
1250
1
0
SYS_CLK = 10 MHz
O
N
P
%err
13
1282
2
0
13
1282
1
0
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