CP3BT23_14 Datasheet, PDF (61/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
10.3.3 External NMI Trap Control and Status Register (EXNMI)
The EXNMI register is a byte-wide read/write register. It indicates the current value of the NMI pin and
controls the NMI interrupt trap generation based on a falling edge of the NMI pin. TST, EN and ENLCK
are cleared on reset. When writing to this register, all reserved bits must be written with 0 for the device to
function properly
7
3
2
1
0
Reserved
ENLCK
PIN
EN
EN
PIN
ENLCK
The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts. The
bit is cleared by hardware at reset and whenever the NMI interrupt occurs (EXNMI.EXT set).
It is intended for applications where the NMI input toggles frequently but nested NMI traps
are not desired. For these applications, the EN bit needs to be re-enabled before exiting the
trap handler. When used this way, the ENLCK bit should never be set. The EN bit can be set
and cleared by software (software can set this bit only if EXNMI.EXT is cleared), and should
only be set after the interrupt base register and the interrupt stack pointer have been set up.
0 – NMI interrupts not enabled by this bit (but may be enabled by the ENLCK bit).
1 – NMI interrupts enabled.
The PIN bit indicates the state (non-inverted) on the NMI input pin. This bit is read-only, data
written into it is ignored.
0 – NMI pin not asserted.
1 – NMI pin asserted.
The EXNMI trap enable lock bit is used to permanently enable NMI interrupts. Only a device
reset can clear the ENLCK bit. This allows the external NMI feature to be enabled after the
interrupt base register and the interrupt stack pointer have been set up. When the ENLCK bit
is set, the EN bit is ignored.
0 – NMI interrupts not enabled by this bit (but may be enabled by the EN bit).
1 – NMI interrupts enabled.
10.3.4 Interrupt Enable and Mask Register 0 (IENAM0)
The IENAM0 register is a word-wide read/write register which holds bits that individually enable and
disable the maskable interrupt sources IRQ1 through IRQ15. The register is initialized to FFFFh at reset.
15
IENA
1
0
Res.
IENA
Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ1
through IRQ15, for example IENA15 controls IRQ15. Because IRQ0 is not used, IENA0 is
ignored.
0 – Interrupt is disabled.
1 – Interrupt is enabled.
10.3.5 Interrupt Enable and Mask Register 1 (IENAM1)
The IENAM1 register is a word-wide read/write register which holds bits that individually enable and
disable the maskable interrupt sources IRQ16 through IRQ31. The register is initialized to FFFFh at reset.
15
IENA
0
IENA
Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ16
through IRQ31, for example IENA31 controls IRQ31
0 – Interrupt is disabled.
1 – Interrupt is enabled.
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Interrupts
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