CP3BT23_14 Datasheet, PDF (192/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Inside the module, a filter engine receives the 8 kHz stream of 16-bit samples and interpolates to generate
a 64 kHz stream of 16-bit samples. This goes into a CVSD encoder which converts the data into a single-
bit delta stream using the CVSD parameters as defined by the Bluetooth specification. There is a similar
path that reverses this process converting the CVSD 64 kHz bit stream into a 64 kHz 16-bit data stream.
The filter engine then decimates this stream into an 8 kHz, 16-bit data stream.
20.2 PCM CONVERSIONS
During conversion between CVSD and PCM, any PCM format changes are done automatically depending
on whether the PCM data is µ-Law, A-Law, or Linear. In addition to this, a separate function can be used
to convert between the various PCM formats as required. Conversion is performed by setting up the
control bit CVCTL1.PCMCONV to define the conversion and then writing to the LOGIN and LINEARIN
registers and reading from the LOGOUT and LINEAROUT registers. There is no delay in the conversion
operation and it does not have to operate at a fixed rate. It will only convert between µ-Law/A-Law and
linear, not directly between µLaw and A-Law. (This could easily be achieved by converting between µ-Law
and linear and between linear and ALaw.)
If a conversion is performed between linear and µ-Law log PCM data, the linear PCM data are treated in
the leftaligned 14-bit linear data format with the two LSBs unused. If a conversion is performed between
linear and A-Law log PCM data, the linear PCM data are treated in the leftaligned 13-bit linear data format
with the three LSBs unused.
If the module is only used for PCM conversions, the CVSD clock can be disabled by clearing the CVSD
Clock Enable bit (CLKEN) in the control register.
20.3 CVSD CONVERSION
The CVSD/PCM converter module transforms either 8-bit logarithmic or 13to 16-bit linear PCM samples at
a fixed rate of 8 ksps. The CVSD to PCM conversion format must be specified by the CVSDCONV control
bits in the CVSD Control register (CVCTRL).
The CVSD algorithm is designed for 2’s complement 16-bit data and is tuned for best performance with
typical voice data. Mild distortion will occur for peak signals greater than -6 dB. The Bluetooth CVSD
standard is designed for best performace with typical voice signals: nominaly -6dB with occasional peaks
to 0dB rather than full-scale inputs. Distortion of signals greater than -6dB is not considered detrimental to
subjective quality tests for voice-band applications and allows for greater clarity for signals below -6dB.
The gain of the input device should be tuned with this in mind.
If required, the RESOLUTION field of the CVCTRL register can be used to optimize the level of the 16-bit
linear input data by providing attenuations (right-shifts with sign extention) of 1, 2, or 3 bits.
Log data is always 8 bit, but to perform the CVSD conversion, the log data is first converted to 16-bit 2’s
complement linear data. A-law and u-law conversion can also slightly affect the optimum gain of the input
data. The CVCTRL.RESOLUTION field can be used to attenuate the data if required.
If the resolution is not set properly, the audio signal may be clipped or have reduced attenuation.
20.4 PCM to CVSD CONVERSION
The converter core reads out the double-buffered PCMIN register every 125 µs and writes a new 16-bit
CVSD data stream into the CVSD Out FIFO every 250 µs. If the PCMIN buffer has not been updated with
a new PCM sample between two reads from the CVSD core, the old PCM data is used again to maintain
a fixed conversion rate. Once a new 16-bit CVSD data stream has been calculated, it is copied into the 8
× 16-bit wide CVSD Out FIFO.
If there are only three empty words (16-bit) left in the FIFO, the nearly full bit (CVNF) is set, and, if
enabled (CVSDINT = 1), an interrupt request is asserted.
If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if enabled (CVSDERRINT = 1), an interrupt
request is asserted. In this case, the CVSD Out FIFO remains unchanged.
192 CVSD/PCM Conversion Module
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