CP3BT23_14 Datasheet, PDF (242/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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WDSDME
The Watchdog Service Data Match Enable bit controls which method is used to service the
Watchdog timer. When clear, Watchdog servicing is accomplished by writing a count value
to the WDCNT register; write operations to the Watchdog Service Data Match (WDSDM)
register are ignored. When set, Watchdog servicing is accomplished by writing the value
5Ch to the WDSDM register.
0 – Write a count value to the WDCNT register to service the Watchdog timer.
1 – Write 5Ch to the WDSDM register to service the Watchdog timer.
24.4.2 Timer and Watchdog Clock Prescaler Register (TWCP)
The TWCP register is a byte-wide, read/write register that specifies the prescaler value used for dividing
the low-frequency clock to generate the T0IN clock. At reset, the nonreserved bits of the register are
cleared. The register format is shown below.
7
3
2
0
Reserved
MDIV
MDIV
Main Clock Divide. This 3-bit field defines the prescaler factor used for dividing the low speed
device clock to create the T0IN clock. The allowed 3-bit values and the corresponding clock
divisors and clock rates are listed below.
MDIV
000
002
010
011
100
101
Other
Table 24-2.
Clock Divisor (fSCLK = 32.768 kHz)
3
2
4
8
16
32
Reserved
T0IN Frequency
2.768 kHz
16.384 kHz
4 8.192 kHz
8 4.096 kHz
16 2.056 kHz
32 1.024 kHz
N/A
24.4.3 TWM Timer 0 Register (TWMT0)
The TWMT0 register is a word-wide, read/write register that defines the T0OUT interrupt rate. At reset,
TWMT0 register is initialized to FFFFh. The register format is shown below.
15
0
PRESET
PRESET The Timer T0 Preset field holds the value used to reload Timer T0 on each underflow.
Therefore, the frequency of the Timer T0 interrupt is the frequency of T0IN divided by
(PRESET+1). The allowed values of PRESET are 0001h through FFFFh.
24.4.4 TWMT0 Control and Status Register (T0CSR)
The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status.
At reset, the non-reserved bits of the register are cleared. The register format is shown below.
7
5
Reserved
4
3
2
1
FRZT0E
WDLTD
T0INTE
TC
0
RST
242 Timing and Watchdog Module
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