CP3BT23_14 Datasheet, PDF (70/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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11.8 EXTERNAL RESET
External reset is triggered by assertion of the RESET input. As with power-on reset, the on-chip 14-bit
counter enforces a minimum reset cycle time.
11.8.1 Simple External Reset
A simple external reset circuit with brown-out and glitch protection based on the LM809 3-Pin
Microprocessor Reset Circuit is shown in Figure 11-5. The LM809 produces a 240-ms logic low reset
pulse when the power supply rises above a threshold voltage. Various reset thresholds are available for
the LM809, however the options for 2.93V and 3.08V are most suitable for a CP3BT23 device operating
from an IOVCC at 3.0V to 3.3V.
IOVCC
IOVCC
LM809
3-Pin Reset
Circuit
CP3BT2x
RESET
GND
DS496
Figure 11-5. Simple External Reset
11.8.2 Manual and SDI External Reset
An external reset circuit based on the LM3724 5-Pin Microprocessor Reset Circuit is shown in Figure 11-6.
The LM3724 produces a 190-ms logic low reset pulse when the power supply rises above a threshold
voltage or a manual reset button is pressed. Various reset thresholds are available for the LM3724,
however the option for 3.08V is most suitable for a CP3BT23 device operating from an IOVCC at 3.3V.
IOVCC
IOVCC
Manual
Reset
LM3724
5-Pin Reset
Circuit
10NŸ
CP3BT2x
RESET
GND
SDI Reset
DS497
Figure 11-6. Manual and SDI External Reset
The LM3724 provides a debounced input for a manual pushbutton reset switch. It also has an open-drain
output which can be used for implementing a wire-OR connection with a reset signal from a serial debug
interface. This circuit is typical of a design to be used in a development or evaluation environment,
however it is a good recommendation for all general CP3BT23 designs. If an SDI interface is not
implemented, an LM3722 with active pullup may be used.
70
Triple Clock and Reset
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