CP3BT23_14 Datasheet, PDF (85/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
13.1.1 Wake-Up Edge Detection Register (WK0EDG)
The WK0EDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU
channels. The WK0EDG register is cleared upon reset, which configures all channels to be triggered on
rising edges. The register format is shown below.
15
0
WKED
WKED
The Wake-Up Edge Detection bits control the edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI15:0 channels, respectively.
0 – Triggered on rising edge (low-to-high transition).
1 – Triggered on falling edge (high-to-low transition).
13.1.2 Wake-Up 1 Edge Detection Register (WK1EDG)
The WK1EDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU
channels. The WK1EDG register is cleared upon reset, which configures all channels to be triggered on
rising edges. The register format is shown below.
15
0
WKED
WKED
The Wake-Up Edge Detection bits control the edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI31:16 channels, respectively.
0 – Triggered on rising edge (low-to-high transition).
1 – Triggered on falling edge (high-to-low transition).
13.1.3 Wake-Up Enable Register (WK0ENA)
The WK0ENA register is a word-wide read/write register that individually enables or disables wake-up
events from the MIWU channels. The WK0ENA register is cleared upon reset, which disables all wake-
up/interrupt channels. The register format is shown below.
15
0
WKEN
WKEN
The Wake-Up Enable bits enable and disable the MIWU channels. The WKEN15:0 bits
correspond to the WUI15:0 channels, respectively.
0 – MIWU channel wake-up events disabled.
1 – MIWU channel wake-up events enabled.
13.1.4 Wake-Up 1 Enable Register (WK1ENA)
The WK1ENA register is a word-wide read/write register that individually enables or disables wake-up
events from the MIWU channels. The WK1ENA register is cleared upon reset, which disables all wake-
up/interrupt channels. The register format is shown below.
15
0
WKEN
WKEN
The Wake-Up Enable bits enable and disable the MIWU channels. The WKEN15:0 bits
correspond to the WUI31:16 channels, respectively.
0 – MIWU channel wake-up events disabled.
1 – MIWU channel wake-up events enabled.
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