CP3BT23_14 Datasheet, PDF (7/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
The ADC is compatible with 4-wire resistive touchscreen applications and is intended to provide the
resolution necessary to support handwriting recognition. Low-ohmic touchscreen drivers are provided
internally on the ADC[3:0] pins. Pendown detection is also provided.
The ADC provides several options for the voltage reference source. The positive reference can be
ADVCC (internal), VREFP, ADC0, or ADC3. The negative reference can be ADVCC (internal), ADC1, or
ADC2.
Two specific analog channel selection modes are supported. These are as follows:
• Allow any specific channel to be selected at one time. The A/D Converter performs the specific
conversion requested and stops.
• Allow any differential channel pair to be selected at one time. The A/D Converter performs the specific
differential conversion requested and stops.
In both Single-Ended and Differential modes, there is the capability to connect the analog multiplexer
output and A/D converter input to external pins. This provides the ability to externally connect a common
filter/signal conditioning circuit for the A/D Converter.
3.13 RANDOM NUMBER GENERATOR
RNG peripheral for use in Trusted Computer Peripheral Applications (TCPA) to improve the authenticity,
integrity, and privacy of Internet-based communication and commerce.
3.14 MICROWIRE/SP
The Microwire/SPI (MWSPI) interface module support synchronous serial communications with other
devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and
16-bit data transfers.
The Microwire interface allows several devices to communicate over a single system consisting of four
wires: serial in, serial out, shift clock, and slave enable. At any given time, the Microwire interface operates
as the master or a slave. The Microwire interface supports the full set of slave select for multi-slave
implementation.
In master mode, the shift clock is generated on-chip under software control. In slave mode, a wake-up out
of a lowpower mode may be triggered using the Multi-Input WakeUp module.
3.15 ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire serial interface compatible with the ACCESS.bus
physical layer. It is also compatible with Intel’s System Management Bus (SMBus) and Philips’ I2C bus.
The ACB module can be configured as a bus master or slave, and it can maintain bidirectional
communications with both multiple master and slave devices.
The ACCESS.bus receiver can trigger a wake-up condition out of the low-power modes through the Multi-
Input WakeUp module.
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