CP3BT23_14 Datasheet, PDF (116/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
PREF_CFG
10
11
Table 16-4. (continued)
PREF Source
ADC0
ADC1
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NREF_CFG The Negative Voltage Reference Configuration field specifies the source of the ADC
negative voltage reference, according to the following table:
PREF_CFG
00
01
10
11
Table 16-5.
PREF Source
Internal (AGND)
Reserved
ADC2
ADC3
MUXOUTEN The MUXOUT Enable bit controls whether the output of the Input Multiplexer is available
externally. In single-ended mode, the MUXOUT0 pin is active and the MUXOUT1 pin is
disabled (TRI-STATE). In differential mode, both MUXOUT0 and MUXOUT1 are active.
0 – MUXOUT0 and MUXOUT1 disabled.
1 – MUXOUT0 and MUXOUT1 enabled.
INTEN
The Interrupt Enable bit controls whether the ADC interrupt (IRQ13) is enabled. When
enabled, the interrupt request is asserted when valid data is available in the ADCRESLT
register. This bit has no effect on the wake_up signal to the MIWU unit (WUI30).
0 – IRQ13 disabled.
1 – IRQ13 enabled.
16.5.2 ADC Auxiliary Configuration Register (ADCACR)
The ADCACR register is used to control the clock configuration and report the status of the ADC module.
The CPU bus master has read/write access to the ADCACR register. After reset, this register is clear.
15
14
13
12
CNVT TRG PRM
Reserved
3
2
1
0
CLKDIV
CLKS
EL
CLKSEL
CLKDIV
The Clock Select bit selects the clock source used by the DELAY2 block to generate the
ADC clock.
0 – ADC clock derived from System Clock.
1 – ADC clock derived from Auxiliary Clock 2.
The Clock Divisor field specifies the divisor applied to System Clock to generate the 12 MHz
clock required by the ADC module. Only the System Clock is affected by this divisor. The
divisor is not used when Auxiliary Clock 2 is selected as the clock source.
CLKDIV
00
01
10
11
Table 16-6.
Clock Divisor
1
2
4
Reserved
116 12-Bit Analog to Digital Converter
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