CP3BT23_14 Datasheet, PDF (118/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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16.5.5 ADC Start Conversion Delay Register (ADCSCDLY)
The ADCSCDLY register controls critical timing parameters for the operation of the ADC module.
15
14
13
ADC_DIV
ADC_DELAY1
5
4
0
ADC_DELAY2
ADC_DELAY2
ADC_DELAY1
ADC_DIV
The ADC Delay 2 field specifies the delay between the ADC module clock source
(either System Clock after a programmable divider or Auxiliary Clock 2) and the ADC
clock. The range of effective values for this field is 0 to 20. Values above 20 produce
the same delay as 20, which is about 42 ns.
The ADC Delay 1 field specifies the number of clock periods by which the trigger event
will be delayed before initiating a conversion. The timebase for this delay is the ADC
clock (12 MHz) divided by the ADC_DIV divisor. The ADC_DELAY1 field has 9 bits,
which corresponds to a maximum delay of 511 clock periods.
The ADC Clock Divisor field specifies the divisor applied to the ADC clock (12 MHz) to
generate the clock used to drive the DELAY1 block. A field value of n results in a
division ratio of n+1. With a module clock of 12 MHz, the maximum delay which can be
provided by ADC_DIV and ADC_DELAY settings is:
(1 / 12 MHz) x 4 x 511 = 170 µs
(14)
16.5.6 ADC Result Register (ADCRESLT)
The ADCRESLT register includes the software-visible end of a 4-word FIFO. Conversion results are
loaded into the FIFO from the 12-bit ADC and unloaded when software reads the ADCRESLT register.
The ADCRESLT register is read-only. With the exception of the PEN_DOWN bit, the fields in this register
are cleared when the register is read.
11
0
ADC-RESULT
15
ADC_DONE
14
ADC_OFLW
13
PEN_DOWN
12
SIGN
ADC_RESULT
SIGN
The ADC Result field holds a 12-bit value for the conversion result. If the ADC_DONE
bit is clear, there is no valid result in this field, and the field will have a value of 0. The
ADC_RESULT field and the SIGN bit together form the software-visible end of the
ADC FIFO.
The Sign bit indicates whether the input has a voltage greater than the + input
(differential mode only). For example if ADCGCR.MUX_CFG is 000b, ADC0 is the +
input and ADC1 is the input. If the voltage on ADC0 is greater than the voltage on
ADC1, the SIGN bit will be 0; if the voltage on ADC0 is less than the voltage on ADC1,
the SIGN bit will be 1. In single-ended mode, this bit always reads as 0.
0 – In differential mode, + input has a voltage greater than the input. In single-ended
mode, this bit is always 0.
1 – In differential mode, input has a voltage greater than the + input.
118 12-Bit Analog to Digital Converter
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