CP3BT23_14 Datasheet, PDF (196/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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20.9.9 CVSD Control Register (CVCTRL)
The CVCTRL register is a 16-bit wide, read/write register that controls the mode of operation and of the
module’s interrupts. At reset, all implemented bits are cleared.
7
DMA PO
6
DMA CI
5
DMA CO
4
CVSD ERRINT
3
CVSD INT
2
PCM INT
1
CLK EN
0
CVEN
15
14
Res.
13
12
RESOLUTION
11
PCMCONV
10
9
CVSDCONV
8
DMAPI
CVEN
The Module Enable bit enables or disables the CVSD conversion module interface.
When the bit is set, the interface is enabled which allows read and write operations to
the rest of the module. When the bit is clear, the module is disabled. When the module
is disabled the status register CVSTAT will be cleared to its reset state.
0 – CVSD module enabled.
1 – CVSD module disabled.
CLKEN
PCMINT
CVSDINT
The CVSD Clock Enable bit enables the 2MHz clock to the filter engine and CVSD
encoders and decoders.
0 – CVSD module clock disabled.
1 – CVSD module clock enabled.
The PCM Interrupt Enable bit controls generation of the PCM interrupt. If set, this bit
enables the PCM interrupt. If the PCMINT bit is clear, the PCM interrupt is disabled.
After reset, this bit is clear.
0 – PCM interrupt disabled.
1 – PCM interrupt enabled.
The CVSD FIFO Interrupt Enable bit controls generation of the CVSD interrupt. If set,
this bit enables the CVSD interrupt that occurs if the CVSD In FIFO is nearly empty or
the CVSD Out FIFO is nearly full. If the CVSDINT bit is clear, the CVSD nearly
full/nearly empty interrupt is disabled. After reset, this bit is clear.
0 – CVSD interrupt disabled.
1 – CVSD interrupt enabled.
CVSDERRINT
DMACO
The CVSD FIFO Error Interrupt Enable bit controls generation of the CVSD error
interrupt. If set, this bit enables an interrupt to occur when the CVSD Out FIFO is full or
the CVSD In FIFO is empty. If the CVSDERRORINT bit is clear, the CVSD full/empty
interrupt is disabled. After reset, this bit is clear.
0 – CVSD error interrupt disabled.
1 – CVSD error interrupt enabled.
The DMA Enable for CVSD Out bit enables hardware DMA control for reading CVSD
data from the CVSD Out FIFO. If clear, DMA support is disabled. After reset, this bit is
clear.
0 – CVSD output DMA disabled.
1 – CVSD output DMA enabled.
DMACI
The DMA Enable for CVSD In bit enables hardware DMA control for writing CVSD data
into the CVSD In FIFO. If clear, DMA support is disabled. After reset, this bit is clear.
0 – CVSD input DMA disabled.
1 – CVSD input DMA enabled.
196 CVSD/PCM Conversion Module
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