CP3BT23_14 Datasheet, PDF (239/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
24 Timing and Watchdog Module
The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic
functions in the system; it also provides Watchdog protection over software execution.
The TWM is designed to provide flexibility in system design by configuring various clock ratios and by
selecting the Watchdog clock source. After setting the TWM configuration, software can lock it for a higher
level of protection against erroneous software action. Once the TWM is locked, only reset can release it.
24.1 TWM STRUCTURE
Figure 24-1 is a block diagram showing the internal structure of the Timing and Watchdog module. There
are two main sections: the Real-Time Timer (T0) section at the top and the Watchdog section on the
bottom.
All counting activities of the module are based on the Slow Clock (SLCLK). A prescaler counter divides
this clock to make a slower clock. The prescaler factor is defined by a 3bit field in the Timer and
Watchdog Prescaler register, which selects either 1, 2, 4, 8, 16, or 32 as the divisor. Therefore, the
prescaled clock period can be 2, 4, 8, 16, or 32 times the Slow Clock period. The prescaled clock signal is
called T0IN.
24.2 TIMER T0 OPERATION
Timer T0 is a programmable 16-bit down counter that can be used as the time base for real-time
operations such as a periodic audible tick. It can also be used to drive the Watchdog circuit.
The timer starts counting from the value loaded into the TWMT0 register and counts down on each rising
edge of T0IN. When the timer reaches zero, it is automatically reloaded from the TWMT0 register and
continues counting down from that value. Therefore, the frequency of the timer is:
f_TIMER = f_SLCLK / (TWTM0 + 1) x prescaler
(33)
When an external crystal oscillator is used as the SLCLK source or when the fast clock is divided
accordingly, f_SLCLK is 32.768 kHz.
The value stored in TWMT0 can range from 0001h to FFFFh.
Slow
Clock
REAL TIME TIMER (T0)
5-Bit Prescaler Counter
(TWCP)
T0IN
TWW/MT0 Register
T0CSR Contrl. Reg.
Restart
16-Bit Timer
(Timer0)
Underflow
T0LINT
(to ICU)
T0OUT
(to Multi-Input-
Wake-Up)
WATCHDOG
Timer
Underflow
Restart
WATCHDOG
Service
Logic
WDSDM
WDCNT
WATCHDOG
Watchdog Error
WDERR
DS080
Figure 24-1. Timing and Watchdog Module Block Diagram
When the counter reaches zero, an internal timer signal called T0OUT is set for one T0IN clock cycle.
This signal sets the TC bit in the TWMT0 Control and Status Register (T0CSR). It also generates an
interrupt (IRQ14), when enabled by the T0CSR.T0INTE bit. T0OUT is also an input to the MIWU (see
Multi-Input Wake-Up), so an edge-triggered interrupt is also available through this alternative mechanism.
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Timing and Watchdog Module 239