CP3BT23_14 Datasheet, PDF (246/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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25.1.2 Clock Source Block
The Clock Source block generates the signals used to clock the two timer/counter registers. The internal
structure of the Clock Source block is shown in Figure 25-2.
Reset
PCLK
Clock
TBn
Prescaler Register
TPRSC_n
5-Bit
Prescaler Counter
Synchr.
No Clock
Prescaled Clock
Pulse Accumulator
External Event
Counter 1
Clock
Select
Counter 1
Clock
Counter 2
Clock
Select
Counter 2
Clock
Slow Clock
Synchr.
Slow Clock
DS449
Figure 25-2. Multi-Function Timer Clock Source
Counter Clock Source SelectThere are two clock source selectors that allow software to independently
select the clock source for each of the two 16-bit counters from any one of the following sources:
• No clock (which stops the counter)
• Prescaled System Clock
• External event count based on TB
• Pulse accumulate mode based on TB
• Slow Clock (derived from the low-frequency oscillator or divided from the high-speed oscillator)
Prescaler The 5-bit clock prescaler allows software to run the timer with a prescaled clock signal. The
prescaler consists of a 5bit read/write prescaler register (TPRSC) and a 5-bit down counter. The System
Clock is divided by the value contained in the prescaler register plus 1. Therefore, the timer clock period
can be set to any value from 1 to 32 divisions of the System Clock period. The prescaler register and
down counter are both cleared upon reset.
External Event ClockThe TB I/O pin can be configured to operate as an external event input clock for
either of the two 16-bit counters. This input can be programmed to detect either rising or falling edges.
The minimum pulse width of the external signal is one System Clock cycle. This means that the maximum
frequency at which the counter can run in this mode is one-half of the System Clock frequency. This clock
source is not available in the capture modes (modes 2 and 4) because the TB pin is used as one of the
two capture inputs.
Pulse Accumulate ModeThe counter can also be configured to count prescaler output clock pulses when
the TB input is high and not count when the TB input is low, as illustrated in Figure 25-3. The resulting
count is an indicator of the cumulative time that the TB input is high. This is called the “pulse-accumulate”
mode. In this mode, an AND gate generates a clock signal for the counter whenever a prescaler clock
pulse is generated and the TB input is high. (The polarity of the TB signal is programmable, so the counter
can count when the TB input is low rather than high.) The pulse-accumulate mode is not available in the
capture modes (modes 2 and 4) because the TB pin is used as one of the two capture inputs
Prescaler
Output
TBn
Counter
Clock
246 Multi-Function Timer
DS450
Figure 25-3. Pulse-Accumulate Mode
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