CP3BT23_14 Datasheet, PDF (68/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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For systems that do not require a reduced power consumption mode, the external crystal network may be
omitted for the Slow Clock. In that case, the Slow Clock can be synthesized by dividing the Main Clock by
a prescaler factor. The prescaler circuit consists of a fixed divide-by-2 counter and a programmable 8-bit
prescaler register. This allows a choice of clock divisors ranging from 2 to 512. The resulting Slow Clock
frequency must not exceed 100 kHz.
A software-programmable multiplexer selects either the prescaled Main Clock or the 32.768 kHz oscillator
as the Slow Clock. At reset, the prescaled Main Clock is selected, ensuring that the Slow Clock is always
present initially. Selection of the 32.768 kHz oscillator as the Slow Clock disables the clock prescaler,
which allows the CLK1 oscillator to be turned off, which reduces power consumption and radiated
emissions. This can be done only if the module detects a toggling low-speed oscillator. If the low-speed
oscillator is not operating, the prescaler remains available as the Slow Clock source.
11.4 PLL Clock
The PLL Clock is generated by the PLL from the 12 MHz Main Clock by applying a multiplication factor of
×3, ×4, or ×5.
To enable the PLL:
1. Set the PLL multiplication factor in PRFSC.MODE.
2. Clear the PLL power-down bit CRCTRL.PLLPWD.
3. Clear the high-frequency clock select bit CRCTRL.FCLK.
4. Read CRCTRL.FCLK, and go back to step 3 if not clear.
The CRCTRL.FCLK bit will be clear only after the PLL has stabilized, so software must repeat step 3
until the bit is clear. The clock source can be switched back to the Main Clock by setting the
CRCTRL.FCLK bit.
The PRSFC register must not be modified while the System Clock is derived from the PLL Clock. The
System Clock must be derived from the low-frequency oscillator clock while the MODE field is
modified.
11.5 System Clock
The System Clock drives most of the on-chip modules, including the CPU. Typically, it is driven by the
Main Clock, but it can also be driven by the PLL. In either case, the clock signal is passed through a
programmable divider (scale factors from ÷1 to ÷16).
11.6 Auxiliary Clocks
Auxiliary Clock 1 and Auxiliary Clock 2 are generated from Main Clock for use by certain peripherals.
Auxiliary Clock 1 is available for the Bluetooth controller and the Advanced Audio Interface. Auxiliary
Clock 2 is available for the CVSD/ PCM transcoder and the 12-bit ADC. The Auxiliary clocks may be
configured to keep these peripherals running when the System Clock is slowed down or suspended during
lowpower modes.
11.7 Power-On Reset
The CP3BT23 has specific Power On Reset (POR) timing requirements that must be met to prevent
corruption of the on-chip flash program and data memories. This timing sequence shown in Figure 11-4.
All reset circuits must ensure that this timing sequence is always maintained during power-up and power-
down. The design of the power supply also affects how this sequence is implemented.
The power-up sequence is:
1. The RESET pin must be held low until both IOVCC and VCC have reached the minimum levels
specified in the DC Characteristics section. IOVCC and VCC are allowed to reach their nominal levels
at the same time which is the best-case scenario.
68
Triple Clock and Reset
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