CP3BT23_14 Datasheet, PDF (18/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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If a general-purpose register is specified by an operation that is 8 bits long, only the lower byte of the
register is used; the upper part is not referenced or modified. Similarly, for word operations on register
pairs, only the lower word is used. The upper word is not referenced or modified.
5.2 DEDICATED ADDRESS REGISTERS
The CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and
INTBASE registers.
5.2.1 Program Counter (PC) Register
The 24-bit value in the PC register points to the first byte of the instruction currently being executed.
CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0.
At reset, the PC is initialized to 0 or an optional predetermined value. When a warm reset occurs, value of
the PC prior to reset is saved in the (R1,R0) general-purpose register pair.
5.2.2 Interrupt Stack Pointer (ISP)
The 32-bit ISP register points to the top of the interrupt stack. This stack is used by hardware to service
exceptions (interrupts and traps). The stack pointer may be accessed as the ISP register for initialization.
The interrupt stack can be located anywhere in the CPU address space. The ISP cannot be used for any
purpose other than the interrupt stack, which is used for automatic storage of the CPU registers when an
exception occurs and restoration of these registers when the exception handler returns. The interrupt
stack grows downward in memory. The least significant bit and the 8 most significant bits of the ISP
register are always 0.
5.2.3 User Stack Pointer (USP)
The USP register points to the top of the user-mode program stack. Separate stacks are available for user
and supervisor modes, to support protection mechanisms for multitasking software. The processor mode
is controlled by the U bit in the PSR register (which is called PSR.U in the shorthand convention). Stack
grow downward in memory. If the USP register points to an illegal address (any address greater than
0x00FF_FFFF) and the USP is used for stack access, an IAD trap is taken.
5.2.4 Interrupt Base Register (INTBASE)
The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be
located anywhere in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0
must written with 0.
5.3 PROCESSOR STATUS REGISTER (PSR)
The PSR provides state information and controls operating modes for the CPU. The format of the PSR is
shown below.
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
I
P
E
O
N
X
F
O
U
L
T
C
C
The Carry bit indicates whether a carry or borrow occurred after addition or subtraction.
0 – No carry or borrow occurred.
1 – Carry or borrow occurred.
T
The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every
instruction. Tracing is automatically disabled during the execution of an exception handler.
0 – Tracing disabled.
1 – Tracing enabled.
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CPU Architecture
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