CP3BT23_14 Datasheet, PDF (67/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Component
Crystal
Capacitor C1, C2
Table 11-1. Component Values of the High Frequency Crystal Circuit
Parameters
Resonance Frequency Type Max. Serial
Resistance Max. Shunt Capacitance Load
Capacitance
Capacitance
Values
12 MHz ± 20 ppm
AT-Cut
50 Ω
7 pF
22 pF
22 pF
Tolerance
N/A
20%
Component
Crystal
Capacitor C1, C2
Table 11-2. Component Values of the Low Frequency Crystal Circuit
Parameters
Resonance Frequency
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Min. Q factor
Capacitance
Values
32.768 kHz
Parallel
N-Cut or XY-bar
40 kΩ
2 pF
12.5 pF
40000
25 pF
Tolerance
N/A
20%
Choose capacitor component values in the tables to obtain the specified load capacitance for the crystal
when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to
8 pF). As a guideline, the load capacitance is:
CL = [(C1 x C2) / (C1+C2)] + Cparasitic
where
• C2 > C1
(1)
C1 can be trimmed to obtain the desired load capacitance. The start-up time of the 32.768 kHz oscillator
can vary from one to six seconds. The long start-up time is due to the high Q value and high serial
resistance of the crystal necessary to minimize power consumption in Power Save mode.
11.2 MAIN CLOCK
The Main Clock is generated by the 12-MHz high-frequency oscillator or driven by an external signal
(typically the LMX5252 RF chip). It can be stopped by the Power Management Module to reduce power
consumption during periods of reduced activity. When the Main Clock is restarted, a 14-bit timer generates
a Good Main Clock signal after a start-up delay of 32,768 clock cycles. This signal is an indicator that the
high-frequency oscillator is stable.
The Stop Main Osc signal from the Power Management Module stops and starts the high-frequency
oscillator. When this signal is asserted, it presets the 14-bit timer to 3FFFh and stops the high-frequency
oscillator. When the signal goes inactive, the high-frequency oscillator starts and the 14-bit timer counts
down from its preset value. When the timer reaches zero, it stops counting and asserts the Good Main
Clock signal.
11.3 SLOW CLOCK
The Slow Clock is necessary for operating the device in reduced power modes and to provide a clock
source for modules such as the Timing and Watchdog Module.
The Slow Clock operates in a manner similar to the Main Clock. The Stop Slow Osc signal from the Power
Management Module stops and starts the low-frequency (32.768 kHz) oscillator. When this signal is
asserted, it presets a 6bit timer to 3Fh and disables the low-frequency oscillator. When the signal goes
inactive, the low-frequency oscillator starts, and the 6-bit timer counts down from its preset value. When
the timer reaches zero, it stops counting and asserts the Good Slow Clock signal, which indicates that the
Slow Clock is stable.
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