CP3BT23_14 Datasheet, PDF (232/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Slave Bus Stall
When operating as a slave, this device stalls the ACCESS.bus by extending the first clock cycle of a
transaction in the following cases:
• The ACBST.SDAST bit is set.
• The ACBST.NMATCH, and ACBCTL1.NMINTE bits are set.
Slave Error Detections
The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition
within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the
BER bit is set and the MATCH and GMATCH bits are cleared, causing the module to be an unaddressed
slave.
Power Down
When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status.
If the ACB is enabled (ACBCTL2.ENABLE = 1) on detection of a Start Condition, a wake-up signal is
issued to the MIWU module. Use this signal to switch this device to Active mode.
The ACB module cannot check the address byte for a match following the start condition that caused the
wake-up event for this device. The ACB responds with a negative acknowledge, and the device should
resend both the Start Condition and the address after this device has had time to wake up.
Check that the ACBCST.BUSY bit is inactive before entering Power Save, Idle, or Halt mode. This
guarantees that the device does not acknowledge an address sent and stop responding later.
23.2.3 SDA and SCL Pins Configuration
The SDA and SCL pins are driven as open-drain signals. For more information, see the I/O configuration
section.
23.2.4 ACB Clock Frequency Configuration
The ACB module permits software to set the clock frequency used for the ACCESS.bus clock. The clock
is set by the ACBCTL2.SCLFRQ field. This field determines the SCL clock period used by this device.
This clock low period may be extended by stall periods initiated by the ACB module or by another
ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be
forced by the other bus master until the conflict is resolved.
23.3 ACCESS.BUS INTERFACE REGISTERS
The ACCESS.bus interface uses the registers listed in Table 23-1.
Name
ACBSDA
ACBST
ACBCST
ACBCTL
ACBCTL2
ACBCTL3
ACBADDR
ACBADDR2
Table 23-1. ACCESS.bus Interface Registers
Address
FF F2A0h
FF F2A2h
FF F2A4h
FF F2A6h
FF F2AAh
FF F2AEh
FF F2A8h
FF F2ACh
Description
ACB Serial Data Register
ACB Status Register
ACB Control Status Register
ACB Control Register 1
ACB Control Register 2
ACB Control Register 3
ACB Own Address Register 1
ACB Own Address Register 2
232 ACCESS.bus Interface
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