CP3BT23_14 Datasheet, PDF (81/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
12.7.5 Software-Controlled Transition to Active Mode
A transition from Power Save mode to Active mode can be accomplished by either a software command
or a hardware wake-up event. The software method is to write a 0 to the PMMCR.PSM bit. The value of
the register bit changes only after the transition to the Active mode is completed.
If the high-frequency oscillator is disabled for Power Save operation, the oscillator must be enabled and
allowed to stabilize before the transition to Active mode. To enable the high-frequency oscillator, software
writes a 0 to the PMMCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit, software must first monitor
the PMMSR.OMC bit to determine when the oscillator has stabilized.
12.7.6 Wake-Up Transition to Active Mode
A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to Active
mode. Hardware wake-up events are:
• • When a wake-up event occurs, the on-chip hardware performs the following steps:
1. Clears the PMMCR.DMC bit, which enables the high-frequency clock (if it was disabled).
2. Waits for the PMMSR.OMC bit to become set, which indicates that the high-frequency clock is
operating and is stable.
3. Clears the PMMCR.DHC bit, which enables the PLL.
4. Waits for the PMMSR.OHC bit to become set.
5. Switches the device into Active mode.
12.7.7 Power Mode Switching Protection
The Power Management Module has several mechanisms to protect the device from malfunctions caused
by missing or unstable clock signals.
The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits indicate the current status of the PLL, high-
frequency oscillator, and low-frequency oscillator, respectively. Software can check the appropriate bit
before switching to a power mode that requires the clock. A set status bit indicates an operating, stable
clock. A clear status bit indicates a clock that is disabled, not available, or not yet stable. (Except in the
case of the PLL, which has a set status bit when disabled.)
During a power mode transition, if there is a request to switch to a mode with a clear status bit, the switch
is delayed until that bit is set by the hardware.
When the system is built without an external crystal network for the low-frequency clock, Main Clock is
divided by a prescaler factor to produce the low-frequency clock. In this situation, Main Clock is disabled
only in the Halt mode, and cannot be disabled for the Power Save or Idle mode.
Without an external crystal network for the low-frequency clock, the device comes out of Halt or Idle mode
and enters Active mode with Main Clock driving Slow Clock.
Note: For correct operation in the absence of a low-frequency crystal, the X2CKI pin must be tied low (not
left floating) so that the hardware can detect the absence of the crystal.
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