CP3BT23_14 Datasheet, PDF (238/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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• The BB bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on
the bus and both devices cease being bus masters at the same time. In this situation, the BB bits of
both devices are active (because each deduces that there is another master currently performing a
transaction, while in fact no device is executing a transaction), and the bus would stay locked until
some device sends a ACBCTL1.STOP condition. The ACBCST.BB bit allows software to monitor bus
usage, so it can avoid sending a STOP signal in the middle of the transaction of some other device on
the bus. This bit detects whether the bus remains unused over a certain period, while the BB bit is set.
• In some cases, the bus may get stuck with the SCL or SDA lines active. A possible cause is an
erroneous Start or Stop Condition that occurs in the middle of a slave receive session. When the SCL
signal is stuck active, there is nothing that can be done, and it is the responsibility of the module that
holds the bus to release it. When the SDA signal is stuck active, the ACB module enables the release
of the bus by using the following sequence. Note that in normal cases, the SCL signal may be toggled
only by the bus master. This protocol is a recovery scheme which is an exception that should be used
only in the case when there is no other master on the bus. The recovery scheme is as follows:
1. Disable and re-enable the module to set it into the not addressed slave mode.
2. Set the ACBCTL1.START bit to make an attempt to issue a Start Condition.
3. Check if the SDA signal is active (low) by reading ACBCST.TSDA bit. If it is active, issue a single SCL
cycle by writing 1 to ACBCST.TGSCL bit. If the SDA line is not active, continue from step 5.
4. Check if the ACBST.MASTER bit is set, which indicates that the Start Condition was sent. If not, repeat
step 3 and 4 until the SDA signal is released.
5. Clear the BB bit. This enables the START bit to be executed. Continue according to “Bus Idle Error
Recovery”.
23.4.1 Avoiding Bus Error During Write Transaction
A Bus Error (BER) may occur during a write transaction if the data register is written at a very specific
time. The module generates one system-clock cycle setup time of SDA to SCL vs. the minimum time of
the clock divider ratio.
The problem can be masked within the driver by dynamically dividing-by-half the SCL width immediately
after the slave address is successfully sent and before writing to the ACBSDA register. This has the effect
of forcing SCL into the stretch state.
The following code example is the relevant segment of the ACCESS.bus driver addressing this issue.
238 ACCESS.bus Interface
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