CP3BT23_14 Datasheet, PDF (74/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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11.9.4 Auxiliary Clock Prescaler Register (PRSAC)
The PRSAC register is a byte-wide read/write register that holds the clock divisor values for prescalers
used to generate the two auxiliary clocks from the Main Clock. The register is initialized to FFh at reset.
7
4
3
0
ACDIV2
ACDIV2
ACDIV1
ACDIV2
The Auxiliary Clock Divisor 1 field specifies the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock is divided by a value of (ACDIV2 + 1).
74
Triple Clock and Reset
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