CP3BT23_14 Datasheet, PDF (292/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
(continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
C_ADCIN
Total Capacitance of ADC
Reference Input⁽¹⁾
C_ADCINS
Switched Capacitance of ADC
Reference Input⁽¹⁾
R_ADCIN
Resistance of ADC Reference Input
Path ⁽¹⁾
29.7 FLASH MEMORY ON-CHIP PROGRAMMING
www.ti.com
MIN
TYP
MAX UNIT
50
100
pF
8
10
pF
0.2
0.6 kohm
29.8 over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t_START
t_TRAN
t_PROG
t_PERASE
t_MERASE
t_END
t_MEND
t_RCV
t_HV
t_HV
Program/Erase to NVSTR Setup
Time⁽¹⁾ (NVSTR = Non-Volatile
Storage
NVSTR to Program Setup Time⁽²⁾
Programming Pulse Width⁽³⁾
Page Erase Pulse Width⁽⁴⁾
Module Erase Pulse Width⁽⁵⁾
NVSTR Hold Time⁽⁶⁾
NVSTR Hold Time (Module Erase)⁽⁷⁾
Recovery Time⁽⁸⁾
Cumulative Program High Voltage 128K program blocks
Period For Each Row After Erase⁽⁹⁾ _{8K data block}
Write/Erase Endurance
10
20
20
200
5
100
1
–
–
20,000
5
–
–
µs
40
µs
–
ms
–
ms
–
µs
–
µs
–
µs
8
ms
4
ms
– cycles
Data Retention
25°C
100
– years
(1) Program/erase to NVSTR Setup Time is determined by the following equation: tSTART = Tclk × (FTDIV + 1) × (FTSTART + 1), where
Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTSTART is the contents of the
FMSTART or FSMSTART register
(2) NVSTR to Program Setup Time is determined by the following equation: tTRAN = Tclk × (FTDIV + 1) × (FTTRAN + 1), where Tclk is the
System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or
FSMTRAN register
(3) Programming Pulse Width is determined by the following equation: tPROG = Tclk × (FTDIV + 1) × 8 × (FTPROG + 1), where Tclk is the
System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or
FSMPROG register
(4) Page Erase Pulse Width is determined by the following equation: tPERASE = Tclk × (FTDIV + 1) × 4096 × (FTPER + 1), where Tclk is
the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or
FSMPERASE register
(5) Module Erase Pulse Width is determined by the following equation: tMERASE = Tclk × (FTDIV + 1) × 4096 × (FTMER + 1), where Tclk
is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0
or FSMMERASE0 register
(6) NVSTR Hold Time is determined by the following equation: tEND = Tclk × (FTDIV + 1) × (FTEND + 1), where Tclk is the System Clock
period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register
(7) NVSTR Hold Time (Module Erase) is determined by the following equation: tMEND = Tclk × (FTDIV + 1) × 8 × (FTMEND + 1), where
Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMEND is the contents of the
FMMEND or FSMMEND register
(8) Recovery Time is determined by the following equation: tRCV = Tclk × (FTDIV + 1) × (FTRCV + 1), where Tclk is the System Clock
period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register
(9) Cumulative program high voltage period for each row after erase tHV is the accumulated duration a flash cell is exposed to the
programming voltage after the last erase cycle.
292 Electrical Characteristics
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