CP3BT23_14 Datasheet, PDF (17/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
5 CPU Architecture
The CP3BT23 uses the CR16C third-generation 16-bit CompactRISC processor core. The CPU
implements a Reduced Instruction Set Computer (RISC) architecture that allows an effective execution
rate of up to one instruction per clock cycle. For a detailed description of the CPU16C architecture, see
the CompactRISC CR16C Programmer’s Reference Manual which is available on the Texas Instruments
web site (http://www.nsc.com).
The CR16C CPU core includes these internal registers:
• General-purpose registers (R0-R13, RA, and SP)
• Dedicated address registers (PC, ISP, USP, and INTBASE)
• Processor Status Register (PSR)
• Configuration Register (CFG)
The R0-R11, PSR, and CFG registers are 16 bits wide. The R12, R13, RA, SP, ISP and USP registers are
32 bits wide. The PC register is 24 bits wide. Figure 5-1shows the CPU registers.
Dedicated Address Registers
23 15
0
General-Purpose Registers
15
0
31
PC
R0
ISPH
ISPL
R1
USPH
USPL
R2
INTBASEH
INTBASEL
R3
R4
R5
Processor Status Register
R6
15
0
R7
PSR
R8
Configuration Register
R9
15
0
R10
CFG
31
R11
R12
R13
RA
SP
DS004
Figure 5-1. CPU Registers
5.1 GENERAL-PURPOSE REGISTERS
The CompactRISC CPU features 16 general-purpose registers. These registers are used individually as
16-bit operands or as register pairs for operations on addresses greater than 16 bits.
• General-purpose registers are defined as R0 through R13, RA, and SP.
• Registers are grouped into pairs based on the setting of the Short Register bit in the Configuration
Register (CFG.SR). When the CFG.SR bit is set, the grouping of register pairs is upward-compatible
with the architecture of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11),
(R13_L, R12_L), (R14_L, R13_L) and SP. (R14_L, R13_L) is the same as (RA,ERA).
• When the CFG.SR bit is clear, register pairs are grouped in the manner used by native CR16C
software: (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP. R12, R13, RA, and SP are
32-bit registers for holding addresses greater than 16 bits.
With the recommended calling convention for the architecture, some of these registers are assigned
special hardware and software functions. Registers R0 to R13 are for generalpurpose use, such as
holding variables, addresses, or index values. The SP register holds a pointer to the program runtime
stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold
base addresses used in the index addressing mode.
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