CP3BT23_14 Datasheet, PDF (220/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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22.1.4 Clocking Modes
Two clocking modes are supported: the normal mode and the alternate mode.
In the normal mode, the output data, which is transmitted on the MDODI pin (master mode) or the MDIDO
pin (slave mode), is clocked out on the falling edge of the shift clock MSK. The input data, which is
received via the MDIDO pin (master mode) or the MDODI pin (slave mode), is sampled on the rising edge
of MSK.
In the alternate mode, the output data is shifted out on the rising edge of MSK on the MDODI pin (master
mode) or MDIDO pin (slave mode). The input data, which is received via MDIDO pin (master mode) or
MDODI pin (slave mode), is sampled on the falling edge of MSK.
The clocking modes are selected with the SCM bit. The SCIDL bit allows selection of the value of MSK
when it is idle (when there is no data being transferred). Various MSK clock frequencies can be
programmed via the MCDV bits. Figure Figure 22-3 through Figure 22-6 show the data transfer timing for
the normal and the alternate modes with the SCIDL bit clear and set.
Note that when data is shifted out on MDODI (master mode) or MDIDO (slave mode) on the leading edge
of the MSK clock, bit 14 (16-bit mode) is shifted out on the second leading edge of the MSK clock. When
data are shifted out on MDODI (master mode) or MDIDO (slave mode) on the trailing edge of MSK, bit 14
(16-bit mode) is shifted out on the first trailing edge of MSK.
22.2 Master Mode
In Master mode, the MSK pin is an output for the shift clock, MSK. When data is written to the MWDAT
register, eight or sixteen MSK clocks, depending on the mode selected, are generated to shift the 8 or 16
bits of data, and then MSK goes idle again. The MSK idle state can be either high or low, depending on
the SCIDL bit.
Figure 22-3. Normal Mode (SCIDL = 0)
220 Microwire/SPI Interface
Figure 22-4. Normal Mode (SCIDL = 1)
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