CP3BT23_14 Datasheet, PDF (33/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
7 System Configuration Registers
The system configuration registers control and provide status for certain aspects of device setup and
operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration
registers are listed in Table 7-1.
Name
MCFG
MSTAT
Table 7-1. System Configuration Registers
Address
FF F910h
FF F914h
Description
Module Configuration Register
Module Status Register
7.1 MODULE CONFIGURATION REGISTER (MCFG)
The MCFG register is a byte-wide, read/write register that selects the clock output features of the device.
The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the
register contents are preserved during all power modes. The MCFG register format is shown below.
7
Res.
6
MEM_IO_
SPEED
5
MISC_IO_
SPEED
4
Res.
3
SCLK OE
2
MCLK OE
1
PLLCLK OE
0
EXI OE
EXIOE
PLLCLKOE
MCLKOE
SCLKOE
MISC_IO_
SPEED
MEM_IO_
SPEED
The EXIOE bit controls whether the external bus is enabled in the IRE environment for
implementing the I/O Zone (FF FB00h–FF FBFFh).
0 – External bus disabled.
1 – External bus enabled.
The PLLCLKOE bit controls whether the PLL clock is driven on the ENV0/PLLCLK pin.
0 – ENV0/PLLCLK pin is high impedance.
1 – PLL clock driven on the ENV0/PLLCLK pin.
The MCLKOE bit controls whether the Main Clock is driven on the ENV1/CPUCLK pin.
0 – ENV1/CPUCLK pin is high impedance.
1 – Main Clock is driven on the ENV1/CPU- CLK pin.
The SCLKOE bit controls whether the Slow Clock is driven on the ENV2/SLOWCLK pin.
0 – ENV2/SLOWCLK pin is high impedance.
1 – Slow Clock is driven on the ENV2/SLOWCLK pin.
The MISC_IO_SPEED bit controls the slew rate of the output drivers for the ENV[2:0],
RDY, RFDATA, and TDO pins. To minimize noise, the slow slew rate is recommended.
0 – Fast slew rate.
1 – Slow slew rate.
The MEM_IO_SPEED bit controls the slew rate of the output drivers for the A[22:0], RD,
SEL[2:0], SELIO, WR[1:0], PB[7:0], and PC[7:0] pins. Memory speeds for the CP3BT23
are characterized with fast slew rate. Slow slew rate reduces the available memory
access time by 5 ns.
0 – Fast slew rate.
1 – Slow slew rate.
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System Configuration Registers
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