CP3BT23_14 Datasheet, PDF (210/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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21.3.6 UART Mode Select Register 1 (UnMDSL1)
The UnMDSL1 register is a byte-wide, read/write register that selects the clock source, synchronization
mode, attention mode, and line break generation. This register is cleared at reset. The register format is
shown below.
7
URTS
6
UFCE
5
UERD
4
UETD
3
UCKS
2
UBRK
1
UATN
0
UMOD
UMOD
UATN
UBRK
UCKS
UETD
UERD
UFCE
URTS
The Mode bit selects between synchronous and asynchronous mode. Synchronous mode is
only available for the UART0 module. 0 – Asynchronous mode. 1 – Synchronous mode.
The Attention Mode bit is used to enable Attention mode. When set, this bit selects the
attention mode of operation for the UART. When clear, the attention mode is disabled. The
hardware clears this bit after an address frame is received. An address frame is a 9-bit
character with a 1 in the ninth bit position.
0 – Attention mode disabled.
1 – Attention mode enabled.
The Force Transmission Break bit is used to force the TXD output low. Setting this bit to 1
causes the TXD pin to go low. TXD remains low until the UBRK bit is cleared by software.
0 – Normal operation.
1 – TXD pin forced low.
The Synchronous Clock Source bit controls the clock source when the UART operates in the
synchronous mode (UMOD = 1). This functionality is only available for the UART0 module. If
the UCKS bit is set, the UART operates from an external clock provided on the CKX pin. If
the UCKS bit is clear, the UART operates from the baud rate clock produced by the UART
on the CKX pin. This bit is ignored when the UART operates in the asynchronous mode.
0 – Internal baud rate clock is used.
1 – External clock is used.
The Enable Transmit DMA bit controls whether DMA is used for UART transmit operations.
Enabling transmit DMA automatically disables transmit interrupts, without regard to the state
of the UETI bit.
0 – Transmit DMA disabled.
1 – Transmit DMA enabled.
The Enable Receive DMA bit controls whether DMA is used for UART receive operations.
Enabling receive DMA automatically disables receive interrupts, without regard to the state of
the UERI bit. Receive error interrupts are unaffected by the UERD bit.
0 – Receive DMA disabled.
1 – Receive DMA enabled.
The Flow Control Enable bit controls whether flow control interrupts are enabled.
0 – Flow control interrupts disabled.
1 – Flow control interrupts enabled.
The Ready To Send bit directly controls the state of the RTS output.
0 – RTS output is high.
1 – RTS output is low.
210 UART Modules
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