CP3BT23_14 Datasheet, PDF (241/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Note: After a restart or Watchdog service through WDCNT, do not enter Power Save mode for a period
equivalent to 5 Slow Clock cycles.
24.4 TWM REGISTERS
The TWM registers controls the operation of the Timing and Watchdog Module. There are six such
registers:
Name
TWCFG
TWCP
TWMT0
T0CSR
WDCNT
WDSDM
Table 24-1. TWM Registers
Address
FF FF20h
FF FF22h
FF FF24h
FF FF26h
FF FF28h
FF FF2Ah
Description
Timer and Watchdog Configuration Register
Timer and Watchdog Clock Prescaler Register
TWM Timer 0 Register
TWMT0 Control and Status Register
Watchdog Count Register
Watchdog Service Data Match Register
24.4.1 Timer and Watchdog Configuration Register (TWCFG)
The TWCFG register is a byte-wide, read/write register that selects the Watchdog clock input and service
method, and also allows the Watchdog registers to be selectively locked. A locked register cannot be read
or written; a read operation returns unpredictable values and a write operation is ignored. Once a lock bit
is set, that bit cannot be cleared until the device is reset. At reset, the non-reserved bits of the register are
cleared. The register format is shown below.
7
6
Res.
5
WDSDME
4
WDCT0I
3
LWDCNT
2
LTWMT0
1
LTWCP
0
LTWCFG
LTWCFG
LTWCP
LTWMT0
LWDCNT
WDCT0I
The Lock TWCFG Register bit controls access to the TWCFG register. When clear, access
to the TWCFG register is allowed. When set, the TWCFG register is locked.
0 – TWCFG register unlocked.
1 – TWCFG register locked.
The Lock TWCP Register bit controls access to the TWCP register. When clear, access to
the TWCP register is allowed. When set, the TWCP register is locked.
0 – TWCP register unlocked.
1 – TWCP register locked.
The Lock TWMT0 Register bit controls access to the TWMT0 register. When clear, access
to the TWMT0 and T0CSR registers are allowed. When set, the TWMT0 and T0CSR
registers are locked.
0 – TWMT0 register unlocked.
1 – TWMT0 register locked.
The Lock LDWCNT Register bit controls access to the LDWCNT register. When clear,
access to the LDWCNT register is allowed. When set, the LDWCNT register is locked.
0 – LDWCNT register unlocked.
1 – LDWCNT register locked.
The Watchdog Clock from T0IN bit selects the clock source for the Watchdog timer. When
clear, the T0OUT signal (the output of Timer T0) is used as the Watchdog clock. When set,
the T0IN signal (the prescaled Slow Clock) is used as the Watchdog clock.
0 – Watchdog timer is clocked by T0OUT.
1 – Watchdog timer is clocked by T0IN.
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Timing and Watchdog Module 241