CP3BT23_14 Datasheet, PDF (92/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Name
PHALT
PHDIR
PHDIN
PHDOUT
PHWPU
PHHDRV
PHALTS
PJALT
PJDIR
PJDIN
PJDOUT
PJWPU
PJHDRV
PJALTS
Table 14-1. Port Registers (continued)
Address
FF F320h
FF F322h
FF F324h
FF F326h
FF F328h
FF F32Ah
FF F32Ch
FF F340h
FF F342h
FF F344h
FF F346h
FF F348h
FF F34Ah
FF F34Ch
Description
Port H Alternate Function Register
Port H Direction Register
Port H Data Input Register
Port H Data Output Register
Port H Weak Pull-Up Register
Port H High Drive Strength Register
Port H Alternate Function Select Register
Port J Alternate Function Register
Port J Direction Register
Port J Data Input Register
Port J Data Output Register
Port J Weak Pull-Up Register
Port J High Drive Strength Register
Port J Alternate Function Select Register
In the descriptions of the ports and port registers, the lowercase letter “x” represents the port designation,
either B, C, E, F, G, H, or J. For example, “PxDIR register” means any one of the port direction registers:
PBDIR, PCDIR, PEDIR, PFDIR, PGDIR, PHDIR, or PJDIR.
All of the port registers are byte-wide read/write registers, except for the port data input registers, which
are read-only registers. Each register bit controls the function of the corresponding port pin. For example,
PGDIR.2 (bit 2 of the PGDIR register) controls the direction of port pin PG2.
14.1.1 Port Alternate Function Register (PxALT)
The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate
function. Each port pin can be controlled independently.
A clear bit in the alternate function register causes the corresponding pin to be used for general-purpose
I/O. In this configuration, the output buffer is controlled by the direction register (PxDIR) and the data
output register (PxDOUT). The input buffer is visible to software as the data input register (PxDIN).
A set bit in the alternate function register (PxALT) causes the corresponding pin to be used for its
peripheral I/O function. When the alternate function is selected, the output buffer data and TRI-STATE
configuration are controlled by signals from the on-chip peripheral device.
A reset operation clears the port alternate function registers, which initializes the pins as general-purpose
I/O ports. This register must be enabled before the corresponding alternate function is enabled.
7
0
PxALT
PxALT
The PxALT bits control whether the corresponding port pins are general-purpose I/O ports
or are used for their alternate function by an on-chip peripheral.
0 – General-purpose I/O selected.
1 – Alternate function selected.
92
Input/Output Ports
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