CP3BT23_14 Datasheet, PDF (6/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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3.8 CAN INTERFACE
Two CAN modules provide Full CAN 2.0B class, CAN serial bus interface for applications that require a
high-speed (up to 1 Mbits per second) or a low-speed interface with CAN bus master capability. The data
transfer between CAN and the CPU is established by 15 memory-mapped message buffers, which can be
individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one
for the first 14 message buffers and another one for the 15th message buffer to provide a basic CAN path.
A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission
requests can be processed automatically by automatic reconfiguration to a receiver after transmission or
by automated transmit scheduling upon reception. In addition, a time stamp counter (16bits wide) is
provided to support real-time applications.
The CAN modules are fast core bus peripherals, which allow single-cycle byte or word read/write access.
A set of diagnostic features (such as loopback, listen only, and error identification) support the
development with the CAN module and provide a sophisticated error management tool.
The CAN receivers can trigger a wake-up condition out of the low-power modes through the Multi-Input
Wake-Up module.
3.9 QUAD UART
Four UART modules support a wide range of programmable baud rates and data formats, parity
generation, and several error detection schemes. The baud rate is generated onchip, under software
control. One UART channel supports hardware flow control, DMA, and USART capability (synchronous
mode).
The UARTs offer a wake-up condition from the low-power modes using the Multi-Input Wake-Up module.
3.10 ADVANCED AUDIO INTERFACE
The audio interface provides a serial synchronous, full-duplex interface to CODECs and similar serial
devices. Transmit and receive paths operate asynchronously with respect to each other. Each path uses
three signals for communication: shift clock, frame synchronization, and data.
When the receiver and transmitter use separate shift clocks and frame sync signals, the interface operates
in its asynchronous mode. Alternatively, the transmit and receive path can share the same shift clock and
frame sync signals for synchronous mode operation.
3.11 CVSD/PCM CONVERSION MODULE
The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD
encoding is as defined in the Bluetooth specification and the PCM data can be 8-bit µ-Law, 8-bit A-Law, or
13-bit to 16-bit Linear.
3.12 12-BIT ANALOG TO DIGITAL CONVERTER
This device contains an 8-channel, multiplexed input, successive approximation, 12-bit Analog-to-Digital
Converter. It supports both Single Ended and Differential modes of operation. The integrated 12-bit ADC
provides the following features:
• 8-channel, multiplexed input
• 4 differential channels
• Single-ended and differential external filtering capability
• 12-bit resolution; 11-bit accuracy
• 15-microsecond conversion time
• Support for 4-wire touchscreen applications
• External start trigger
• Programmable start delay after start trigger
• Poll or interrupt on done
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