CP3BT23_14 Datasheet, PDF (199/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
21 UART Modules
The CP3BT23 provides four UART modules. Each UART module is a full-duplex Universal Asynchronous
Receiver/ Transmitter that supports a wide range of software-programmable baud rates and data formats.
It handles automatic parity generation and several error detection schemes.
All UART modules offer the following features:
• Full-duplex double-buffered receiver/transmitter
• Asynchronous operation
• Programmable baud rate
• Programmable framing formats: 7, 8, or 9 data bits; even, odd, or no parity; one or two stop bits (mark
or space)
• Hardware parity generation for data transmission and parity check for data reception
• Interrupts on “transmit ready” and “receive ready” conditions, separately enabled
• Software-controlled break transmission and detection
• Internal diagnostic capability
• Automatic detection of parity, framing, and overrun errors
One module, UART0, offers the following additional features:
• Synchronous operation using the CKX external clock pin
• Hardware flow control (CTS and RTS signals)
• DMA capability
21.1 FUNCTIONAL OVERVIEW
Figure 21-1 is a block diagram of the UART module showing the basic functional units in the UART:
• Transmitter
• Receiver
• Baud Rate Generator
• Control and Error Detection
The Transmitter block consists of an 8-bit transmit shift register and an 8-bit transmit buffer. Data bytes
are loaded in parallel from the buffer into the shift register and then shifted out serially on the TXD pin.
The Receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. Data is received
serially on the RXD pin and shifted into the shift register. Once eight bits have been received, the contents
of the shift register are transferred in parallel to the receive buffer.
The Transmitter and Receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-
bit and loopback operating modes.
The Baud Rate Generator generates the clock for the synchronous and asynchronous operating modes. It
consists of two registers and a two-stage counter. The registers are used to specify a prescaler value and
a baud rate divisor. The first stage of the counter divides the UART clock based on the value of the
programmed prescaler to create a slower clock. The second stage of the counter creates the baud rate
clock by dividing the output of the first stage based on the programmed baud rate divisor.
The Control and Error Detection block contains the UART control registers, control logic, error detection
circuit, parity generator/checker, and interrupt generation logic. The control registers and control logic
determine the data format, mode of operation, clock source, and type of parity used. The error detection
circuit generates parity bits and checks for parity, framing, and overrun errors.
The Flow Control Logic block provides the capability for hardware handshaking between the UART and a
peripheral device. When the peripheral device needs to stop the flow of data from the UART, it de-asserts
the clear-to-send (CTS) signal which causes the UART to pause after sending the current frame (if any).
The UART asserts the ready-to-send (RTS) signal to the peripheral when it is ready to send a character.
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