CP3BT23_14 Datasheet, PDF (173/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
19.3 BIT CLOCK GENERATION
An 8-bit prescaler is provided to divide the audio interface input clock down to the required bit clock rate.
Software can choose between two input clock sources, a primary and a secondary clock source.
On the CP3BT23, the two optional input clock sources are the 12-MHz Aux1 clock (also used for the
Bluetooth LLC) and the 48-MHz PLL output clock. The input clock is divided by the value of the prescaler
BCPRS[7:0] + 1 to generate the bit clock.
The bit clock rate f_bit can be calculated by the following equation:
f_bit = n x f_Sample x Data Length
where
•
(17)
n = Number of slots per Frame
(18)
f_Sample = Sample Frequency in Hz
(19)
Data Length = Length of data word in multiples of 8 bits
(20)
The ideal required prescaler value P_ideal can be calculated as follows:
P_ideal = f_{Audio In} / f_bit
(21)
The real prescaler must be set to an integer value, which should be as close as possible to the ideal
prescaler value, to minimize the bit clock error, f_{bit_error}.
f_{bit_error} [%] = (f_bit f_{Audio In}/P_real) / f_bit x 100
(22)
Example:
The audio interface is used to transfer 13-bit linear PCM data for one audio channel at a sample rate of 8k
samples per second. The input clock of the audio interface is 12 MHz. Furthermore, the codec requires a
minimum bit clock of 256 kHz to operate properly. Therefore, the number of slots per frame must be set to
2 (network mode) although actually only one slot (slot 0) is used. The codec and the audio interface will
put their data transmit pins in TRI-STATE mode after the PCM data word has been transferred. The
required bit clock rate fbit can be calculated by the following equation:
f_bit = n x f_Sample x Data Length = 2 x 8 kHz x 16 = 256 kHz
(23)
The ideal required prescaler value Pideal can be calculated as follows:
P_ideal = f_{Audio In} / f_bit = 12 MHz / 256 kHz = 46.875
(24)
Therefore, the real prescaler value is 47. This results in a bit clock error equal to:
f_{bit_error} = (f_bit f_{Audio In} / P_real) / f_bit x 100 = (256 kHz 12 MHz / 47) / 256 kHz x 100 = 0.27%
(25)
19.4 FRAME CLOCK GENERATION
The clock for the frame synchronization signals is derived from the bit clock of the audio interface. A 7-bit
prescaler is used to divide the bit clock to generate the frame sync clock for the receive and transmit
operations. The bit clock is divided by FCPRS + 1. In other words, the value software must write into the
ACCR.FCPRS field is equal to the bit number per frame minus one. The frame may be longer than the
valid data word but it must be equal to or larger than the 8or 16-bit word. Even if 13-, 14-, or 15-bit data is
being used, the frame width must always be at least 16 bits wide.
In addition, software can specify the length of a long frame sync signal. A long frame sync signal can be
either 6, 13, 14, 15, or 16 bits long, depending on the external codec being used. The frame sync length
can be configured by the Frame Sync Length field (FSL) in the AGCR register
Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CP3BT23
Advanced Audio Interface 173