CP3BT23_14 Datasheet, PDF (181/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
To connect the AAI to an ISDN controller through an IOM-2 compatible interface, the AAI needs to be
configured in this way:
• The AAI must be in IOM-2 Mode (AGCR.IOM2 = 1).
• The AAI operates in synchronous mode (AGCR.ASS = 0).
• The AAI operates as a slave, therefore the bit clock and frame sync source selection must be set to
external (ACGR.IEFS = 1, ACGR.IEBC = 1).
• The frame sync length must be set to long frame sync (ACGR.FSS = 1).
• The data word length must be set to 16-bit (AGCR.DWL = 1).
• The AAI must be set to normal mode (AGCR.SCS[1:0] = 0).
• The internal frame rate must be 8 ksps (ACCR = 00BE).
19.6.5 Loopback Mode
In loopback mode, the STD and SRD pins are internally connected together, so data shifted out through
the ATSR register will be shifted into the ARSR register. This mode may be used for development, but it
also allows testing the transmit and receive path without external circuitry, for example during Built-In-Self-
Test (BIST).
19.6.6 Freeze Mode
The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface
while a development system examines the contents of the FIFOs and registers.
When the FREEZE input is asserted, the audio interface behaves as follows:
• The receive FIFO or receive DMA registers are not updated with new data.
• The receive status bits (RXO, RXE, RXF, and RXAF) are not changed, even though the receive FIFO
or receive DMA registers are read.
• The transmit shift register (ATSR) is not updated with new data from the transmit FIFO or transmit
DMA registers.
• The transmit status bits (TXU, TXF, TXE, and TXAE) are not changed, even though the transmit FIFO
or transmit DMA registers are written.
The time at which these registers are frozen will vary because they operate from a different clock than the
one used to generate the freeze signal.
19.7 AUDIO INTERFACE REGISTERS
Name
ARFR
ARDR0
ARDR
ARDR2
ARDR3
ATFR
Table 19-1. Audio Interface Registers
Address
FF FD40h
FF FD42h
FF FD44h
FF FD46h
FF FD48h
FF FD4Ah
Description
Audio Receive FIFO Register
Audio Receive DMA Register 0
Audio Receive DMA Register 1
Audio Receive DMA Register 2
Audio Receive DMA Register 3
Audio Transmit FIFO Register
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Advanced Audio Interface 181