CP3BT23_14 Datasheet, PDF (197/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
DMAPO
The DMA Enable for PCM Out bit enables hardware DMA control for reading PCM data
from the PCMOUT register. If clear, DMA support is disabled. After reset, this bit is
clear.
0 – PCM output DMA disabled.
1 – PCM output DMA enabled.
DMAPI
The DMA Enable for PCM In bit enables hardware DMA control for writing PCM data
into the PCMIN register. If cleared, DMA support is disabled. After reset, this bit is clear.
0 – PCM input DMA disabled.
CVSDCONV
1 – PCM input DMA enabled.
The CVSD to PCM Conversion Format field specifies the PCM format for CVSD/PCM
conversions. After reset, this field is clear.
00 – CVSD <-> 8-bit µ-Law PCM.
01 – CVSD <-> 8-bit A-Law PCM.
10 – CVSD <-> Linear PCM.
11 – Reserved.
PCMCONV
The PCM to PCM Conversion Format bit selects the PCM format for PCM/PCM
conversions.
0 – Linear PCM <-> 8-bit µ-Law PCM
RESOLUTION
1 – Linear PCM <-> 8-bit A-Law PCM
The Linear PCM Resolution field specifies the attenuation of the PCM data for the linear
PCM to CVSD conversions by right shifting and sign extending the data. This affects the
log PCM data as well as the linear PCM data. The log data is converted to either left-
justified zero-stuffed 13-bit (A-law) or 14-bit (u-law). The RESOLUTION field can be
used to compensate for any change in average levels resulting from this conversion.
After reset, these two bits are clear.
00 – No shift.
01 – 1-bit attentuation.
10 – 2-bit attentuation.
11 – 3-bit attentuation.
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CVSD/PCM Conversion Module 197