CP3BT23_14 Datasheet, PDF (44/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
8.5.4 Flash Memory 1 Write Enable Register (FM1WER)
The FM1WER register controls write protection for the second half of the program flash memory. The data
block is divided into 16 8K-byte sections. Each bit in the FM1WER register controls write protection for
one of these sections. The FM1WER register is cleared after device reset, so the flash memory is write
protected after reset. The CPU bus master has read/write access to this registers.
15
0
FM1WE
FM1WEn The Flash Memory 1 Write Enable n bits control write protection for a section of a flash
memory data block. The address mapping of the register bits is shown below.
Bit
0
1-14
15
Logical Address Range
02 0000h–02 1FFFh
...
03 E000h–03 FFFFh
8.5.5 Flash Data Memory 0 Write Enable Register (FSM0WER)
The FSM0WER register controls write protection for the flash data memory. The data block is divided into
16 512byte sections. Each bit in the FSM0WER register controls write protection for one of these sections.
The FSM0WER register is cleared after device reset, so the flash memory is write protected after reset.
The CPU bus master has read/ write access to this registers.
15
0
FSM0WE
FSM0WEn The The Flash Data Memory 0 Write Enable n bits control write protection for a section of a
flash memory data block. The address mapping of the register bits is shown below.
Bit
0
1-14
15
Logical Address Range
0D 0000h–0D 01FFh
...
0D 1E00h–0D 1FFFh
8.5.6 Flash Memory Control Register (FMCTRL/ FSMCTRL)
This register controls the basic functions of the Flash program memory. The register is clear after device
reset. The CPU bus master has read/write access to this register.
7
MER
6
PER
5
4
3
2
PE
IENPROG
DISVRF
Res
1
CWD
0
LOWPRW
LOWPRW
The Low Power Mode controls whether flash program memory is operated in low-power
mode, which draws less current when data is read. This is accomplished be only accessing
the flash program memory during the first half of the clock period. The low-power mode
must not be used at System Clock frequencies above 25 MHz, otherwise a read access
may return undefined data. This bit must not be changed while the flash program memory is
busy being programmed or erased.
0 – Normal mode.
1 – Low-power mode.
44
Flash Memory
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated