CP3BT23_14 Datasheet, PDF (69/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
2. After both of these supply voltage rails have met this condition, then the RESET pin may be driven
high. At power-up an internal 14-bit counter is set to 3FFFh and begins counting down to 0 after the
crystal oscillator becomes stable. When this counter reaches 0, the onchip RESET signal is driven high
unless the external RESET pin is still being held low. This prevents the CP3BT23 from coming out of
reset with an unstable clock source.
The power-down sequence is:
1. The RESET pin must be driven low as soon as either the IOVCC or VCC voltage rail reaches the
minimum The external reset circuits presented in the following sections provide varying levels of
additional fault tolerance and expandability and are presented as possible examples of solutions to be
used with the CP3BT23. It is important to note, however, that any design for the reset circuit and
power supply must meet the timing requirements shown in Figure 11-4. 2.25V IOVCC 2.25V Core VCC
RESET Main Clock Power Up Power Down DS515 Figure 11-4. Power-On Reset Timing 11.8
EXTERNAL RESET External reset is triggered by assertion of the RESET input. As with power-on
reset, the on-chip 14-bit counter enforces a minimum reset cycle time. 11.8.1 Simple External Reset A
simple external reset circuit with brown-out and glitch protection based on the LM809 3-Pin
Microprocessor Reset Circuit is shown in Figure 11-5. The LM809 produces a 240-ms logic low reset
pulse when the power supply rises above a threshold voltage. Various reset thresholds are available
for the LM809, however the options for 2.93V and 3.08V are most suitable for a CP3BT23 device
operating from an IOVCC at 3.0V to 3.3V. IOVCC IOVCC CP3BT2x LM809 levels specified in the DC
Characteristics.
2. The RESET pin must then be held low until the Main Clock is stopped. The Main Clock will decay with
the same profile as IOVCC.
Meeting the power-down reset conditions ensures that software will not be executed at voltage levels that
may cause 3-Pin Reset Circuit RESET GND DS496 incorrect program execution or corruption of the flash
memories. This situation must be avoided because the Main Clock decays with the IOVCC supply rather
than stopping immediately when IOVCC falls below the minimum specified level.
The external reset circuits presented in the following sections provide varying levels of additional fault
tolerance and expandability and are presented as possible examples of solutions to be used with the
CP3BT23. It is important to note, however, that any design for the reset circuit and power supply must
meet the timing requirements shown in Figure 11-4.
IOVCC
2.25V
Core VCC
2.25V
RESET
Main
Clock
Power Up
Power Down
DS515
Figure 11-4. Power-On Reset Timing
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Triple Clock and Reset
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