CP3BT23_14 Datasheet, PDF (50/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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9 DMA Controller
The DMA Controller (DMAC) has a register-based programming interface, as opposed to an interface
based on I/O control blocks. After loading the registers with source and destination addresses, as well as
block size and type of operation, a DMAC channel is ready to respond to DMA transfer requests. A
request can only come from on-chip peripherals or software, not external peripherals. On receiving a DMA
transfer request, if the channel is enabled, the DMAC performs the following operations:
1. Arbitrates to become master of the CPU bus.
2. Determines priority among the DMAC channels, one clock cycle before T1 of the DMAC transfer cycle.
(T1 is the first clock cycle of the bus cycle.) Priority among the DMAC channels is fixed in descending
order, with Channel 0 having the highest priority.
3. Executes data transfer bus cycle(s) selected by the values held in the control registers of the channel
being serviced, and according to the accessed memory address. The DMAC acknowledges the
request during the bus cycle that accesses the requesting device.
4. If the transfer of a block is terminated, the DMAC does the following:
– Updates the termination bits.
– Generates an interrupt (if enabled).
– Goes to step 6.
5. If DMRQn is still active, and the Bus Policy is “continuous”, returns to step 3.
6. Returns mastership of the CPU bus to the CPU.
Each DMAC channel can be programmed for direct (flyby) or indirect (memory-to-memory) data transfers.
Once a DMAC transfer cycle is in progress, the next transfer request is sampled when the DMAC
acknowledge is de-asserted, then on the rising edge of every clock cycle.
The configuration of either address freeze or address update (increment or decrement) is independent of
the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All
these can be configured for each channel by programming the appropriate control registers.
Each DMAC channel has eight control registers. DMAC channels are described hereafter with the suffix n,
where n = 0 to 3, representing the channel number in the register names.
9.1 CHANNEL ASSIGNMENT
Table 9-1 shows the assignment of the DMA channels to different tasks. Four channels can be shared by
a primary and an secondary function. However, only one source at a time can be enabled. If a channel is
used for memory block transfers, other resources must be disabled.
Channel
0 (Primary)
0 (Secondary)
1 (Primary)
1 (Secondary)
2 (Primary)
2 (Secondary)
3 (Primary)
3 (Secondary)
Table 9-1. DMA Channel Assignment
Peripheral
Reserved
USART
USART
Reserved
Audio Interface
CVSD/PCM Transcoder
Audio Interface
CVSD/PCM Transcoder
Transaction
N/A
R
W
N/A
R
R
W
W
Register
N/A
RXBUF
TXBUF
N/A
ARDR0
PCMOUT
ATDR0
PCMIN
50
DMA Controller
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